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authorJulius Werner <jwerner@chromium.org>2019-08-12 16:45:21 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-08-22 10:36:22 +0000
commitdb7f6fb75282a305c2b0f5540d2f7be939f20dde (patch)
tree2c4fc9e51c6c38c9d7a10a91083c961fd914471e /src/device
parent54ff1a0ad3bb3c1c4bc5283aaf2f03b17c3b25f1 (diff)
downloadcoreboot-db7f6fb75282a305c2b0f5540d2f7be939f20dde.tar.xz
Add buffer_to/from_fifo32(_prefix) helpers
Many peripheral drivers across different SoCs regularly face the same task of piping a transfer buffer into (or reading it out of) a 32-bit FIFO register. Sometimes it's just one register, sometimes a whole array of registers. Sometimes you actually transfer 4 bytes per register read/write, sometimes only 2 (or even 1). Sometimes writes need to be prefixed with one or two command bytes which makes the actual payload buffer "misaligned" in relation to the FIFO and requires a bunch of tricky bit packing logic to get right. Most of the times transfer lengths are not guaranteed to be divisible by 4, which also requires a bunch of logic to treat the potential unaligned end of the transfer correctly. We have a dozen different implementations of this same pattern across coreboot. This patch introduces a new family of helper functions that aims to solve all these use cases once and for all (*fingers crossed*). Change-Id: Ia71f66c1cee530afa4c77c46a838b4de646ffcfb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/device')
-rw-r--r--src/device/Makefile.inc5
-rw-r--r--src/device/mmio.c55
2 files changed, 60 insertions, 0 deletions
diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc
index baa45bec3e..966ca0d198 100644
--- a/src/device/Makefile.inc
+++ b/src/device/Makefile.inc
@@ -53,3 +53,8 @@ verstage-y += i2c.c
romstage-y += i2c.c
ramstage-y += i2c.c
ramstage-y += i2c_bus.c
+
+bootblock-y += mmio.c
+verstage-y += mmio.c
+romstage-y += mmio.c
+ramstage-y += mmio.c
diff --git a/src/device/mmio.c b/src/device/mmio.c
new file mode 100644
index 0000000000..61a1130604
--- /dev/null
+++ b/src/device/mmio.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <device/mmio.h>
+
+/* Helper functions for various MMIO access patterns. */
+
+void buffer_from_fifo32(void *buffer, size_t size, void *fifo,
+ int fifo_stride, int fifo_width)
+{
+ u8 *p = buffer;
+ int i, j;
+
+ assert(fifo_width > 0 && fifo_width <= sizeof(u32) &&
+ fifo_stride % sizeof(u32) == 0);
+
+ for (i = 0; i < size; i += fifo_width, fifo += fifo_stride) {
+ u32 val = read32(fifo);
+ for (j = 0; j < MIN(size - i, fifo_width); j++)
+ *p++ = (u8)(val >> (j * 8));
+ }
+}
+
+void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size,
+ void *fifo, int fifo_stride, int fifo_width)
+{
+ u8 *p = buffer;
+ int i, j = prefsz;
+
+ assert(fifo_width > 0 && fifo_width <= sizeof(u32) &&
+ fifo_stride % sizeof(u32) == 0 && prefsz <= fifo_width);
+
+ uint32_t val = prefix;
+ for (i = 0; i < size; i += fifo_width, fifo += fifo_stride) {
+ for (; j < MIN(size - i, fifo_width); j++)
+ val |= *p++ << (j * 8);
+ write32(fifo, val);
+ val = 0;
+ j = 0;
+ }
+
+}