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authorJustin TerAvest <teravest@google.com>2018-01-17 16:36:30 -0800
committerMartin Roth <martinroth@google.com>2018-01-25 16:50:17 +0000
commitca2ed9f450682c5f23ee1f3affac8b6dba7fdc0b (patch)
tree6c73b52c016bf59eee8d6371793ef479aa75595b /src/device
parent4eaf0fa1550805ba9f3c24fb8675a6e77bd40101 (diff)
downloadcoreboot-ca2ed9f450682c5f23ee1f3affac8b6dba7fdc0b.tar.xz
sconfig: Add a new mmio resource type
Add support for a mmio resource in the devicetree to allow memory-mapped IO addresses to be assigned to given values. AMD platforms perform a significant amount of configuration through these MMIO addresses, including I2C bus configuration. BUG=b:72121803 Change-Id: I5608721c22c1b229f527815b5f17fff3a080c3c8 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/device')
-rw-r--r--src/device/device_util.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/device/device_util.c b/src/device/device_util.c
index 6ccf02cc05..6bc2730143 100644
--- a/src/device/device_util.c
+++ b/src/device/device_util.c
@@ -257,6 +257,7 @@ u32 dev_path_encode(struct device *dev)
ret |= dev->path.spi.cs;
break;
case DEVICE_PATH_NONE:
+ case DEVICE_PATH_MMIO: /* don't care */
default:
break;
}
@@ -332,6 +333,10 @@ const char *dev_path(struct device *dev)
snprintf(buffer, sizeof (buffer), "SPI: %02x",
dev->path.spi.cs);
break;
+ case DEVICE_PATH_MMIO:
+ snprintf(buffer, sizeof (buffer), "MMIO: %08x",
+ dev->path.mmio.addr);
+ break;
default:
printk(BIOS_ERR, "Unknown device path type: %d\n",
dev->path.type);
@@ -406,6 +411,9 @@ int path_eq(struct device_path *path1, struct device_path *path2)
case DEVICE_PATH_SPI:
equal = (path1->spi.cs == path2->spi.cs);
break;
+ case DEVICE_PATH_MMIO:
+ equal = (path1->mmio.addr == path2->mmio.addr);
+ break;
default:
printk(BIOS_ERR, "Unknown device type: %d\n", path1->type);
break;