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authorJohn Zhao <john.zhao@intel.com>2020-05-04 15:58:48 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-06-08 06:39:01 +0000
commit95b4ece0fe4a0855f20bfb7bdf868c56f6b41ae6 (patch)
treead67c6693272ec9495a5c98e44d79e67dd49c3e1 /src/device
parentaaebfa800c002b778ccac8d15d4054778e85b5f0 (diff)
downloadcoreboot-95b4ece0fe4a0855f20bfb7bdf868c56f6b41ae6.tar.xz
device: Add a disabling PCIe device bus master function
A function pci_dev_disable_bus_master() is created. This function can be used to disable Thunderbolt PCIe root ports, bridges and devices for Vt-d based security platform at end of boot service. BUG=None TEST=Verified PCIe device bus master enable bit is cleared. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ie92a15bf2c66fdc311098acb81019d4fb7f68313 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/device')
-rw-r--r--src/device/pci_device.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index f83520e079..032e15c669 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -1643,4 +1643,9 @@ void pci_assign_irqs(struct device *dev, const unsigned char pIntAtoD[4])
#endif
}
}
+
+void pci_dev_disable_bus_master(const struct device *dev)
+{
+ pci_update_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER, 0x0);
+}
#endif