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authorKenji Chen <kenji.chen@intel.com>2015-01-30 13:57:42 +0800
committerPatrick Georgi <pgeorgi@google.com>2015-03-23 13:11:18 +0100
commita874a7c26f7f0477b13428bf6e7405e52b3983f6 (patch)
treee3cc13589de903b2bd300d8d9083ea48d9a352f7 /src/device
parent31c6e632cf607ad8364c49b934f726ef02486d46 (diff)
downloadcoreboot-a874a7c26f7f0477b13428bf6e7405e52b3983f6.tar.xz
PCIe: Revise L1 Sub-State support
BRANCH=None BUG=None TEST=Confirmed build pass only Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: Ic0e845436614e63ad5ace7fb74400f7ea295571c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d3670b92e40d8757a48add6116a0edcec18074d8 Original-Change-Id: I5e029b0f82a771149d4c6127e30b9062e8eaba89 Original-Reviewed-on: https://chromium-review.googlesource.com/244514 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/8833 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/device')
-rw-r--r--src/device/pciexp_device.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index 2bc991cd4b..5e1f114162 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -241,20 +241,17 @@ static void pciexp_L1_substate_commit(device_t root, device_t dev,
pcie_update_cfg(root, root_cap + 0x08, ~0xe3ff0000,
(1 << 21) | (1 << 23) | (1 << 30));
- pcie_update_cfg(root, root_cap + 0x08, ~0xf,
+ pcie_update_cfg(root, root_cap + 0x08, ~0x1f,
L1SubStateSupport);
for (dev_t = dev; dev_t; dev_t = dev_t->sibling) {
- pcie_update_cfg(dev_t, end_cap + 0x08, ~0xff00,
- (comm_mode_rst_time << 8));
-
pcie_update_cfg(dev_t, end_cap + 0x0c , 0xffffff04,
(endp_power_on_value << 3) | (power_on_scale));
pcie_update_cfg(dev_t, end_cap + 0x08, ~0xe3ff0000,
(1 << 21) | (1 << 23) | (1 << 30));
- pcie_update_cfg(dev_t, end_cap + 0x08, ~0xf,
+ pcie_update_cfg(dev_t, end_cap + 0x08, ~0x1f,
L1SubStateSupport);
pciexp_enable_ltr(dev_t);