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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-06-18 22:01:07 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-06-22 07:35:21 +0200 |
| commit | 83fa169101e732b35a36f19624979b378a06f3f5 (patch) | |
| tree | d4a2068a70a24a0d7605ac414200579df156afc7 /src/device | |
| parent | 0e7b7bb6b3180749c7a799a5beecbf0716a49f93 (diff) | |
| download | coreboot-83fa169101e732b35a36f19624979b378a06f3f5.tar.xz | |
oprom: Fix for 64bit
Change-Id: If4c1ab5ae33a64be3e7b14150d410edd291ee4ed
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10591
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/device')
| -rw-r--r-- | src/device/oprom/realmode/x86.c | 2 | ||||
| -rw-r--r-- | src/device/pci_rom.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 485d1a4e42..14bcbc0134 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -188,7 +188,7 @@ static void setup_realmode_idt(void) for (i = 0; i < 256; i++) { idts[i].cs = 0; idts[i].offset = 0x1000 + (i * __idt_handler_size); - write_idt_stub((void *)((u32 )idts[i].offset), i); + write_idt_stub((void *)((uintptr_t)idts[i].offset), i); } /* Many option ROMs use the hard coded interrupt entry points in the diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 26cd6cfb9c..80b2a51a8f 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -57,7 +57,7 @@ struct rom_header *pci_rom_probe(struct device *dev) printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n", dev_path(dev), rom_header); } else { - u32 rom_address; + uintptr_t rom_address; rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); |