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authorDuncan Laurie <dlaurie@chromium.org>2011-10-25 14:15:11 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-03-29 22:16:07 +0200
commit90dcdd43ee83b12ddd1cdafba7613971cbfa2117 (patch)
treea86c9e122215b93566e9f9174e8919f81b08a813 /src/devices/Kconfig
parent22c0468d3927a370b9723e9e78714c2731d33a81 (diff)
downloadcoreboot-90dcdd43ee83b12ddd1cdafba7613971cbfa2117.tar.xz
Add support for enabling PCIe Common Clock and ASPM
These are guarded by individual Kconfig entries. The deprecated CONFIG_PCIE_TUNING defines have been removed in favor of using specific config options. This is the generic half, there is board-specific pieces still to come that tune before and after ASPM is enabled. Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/735 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/devices/Kconfig')
-rw-r--r--src/devices/Kconfig14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/devices/Kconfig b/src/devices/Kconfig
index a731f44aad..5168819519 100644
--- a/src/devices/Kconfig
+++ b/src/devices/Kconfig
@@ -163,3 +163,17 @@ config AGP_PLUGIN_SUPPORT
config CARDBUS_PLUGIN_SUPPORT
bool
default y
+
+config PCIEXP_COMMON_CLOCK
+ prompt "Enable PCIe Common Clock"
+ bool
+ default n
+ help
+ Detect and enable Common Clock on PCIe links.
+
+config PCIEXP_ASPM
+ prompt "Enable PCIe ASPM"
+ bool
+ default n
+ help
+ Detect and enable ASPM on PCIe links.