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authorRonald G. Minnich <rminnich@gmail.com>2006-06-22 04:37:27 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-06-22 04:37:27 +0000
commit88fb1a6c371c9f368157bdb907f70d46bb670311 (patch)
treee15de2e82954df04eeacd055471c278c93b55f4f /src/devices/pci_device.c
parent9d0b30dd2b33d04859986be85b125c3005b2a277 (diff)
downloadcoreboot-88fb1a6c371c9f368157bdb907f70d46bb670311.tar.xz
set up interrupt values for the southbridge, and add a function to
manage them. Make pci_level_irq global. Add value settings for OLPC rev_a board. Comment out no-longer-needed code in olpc mainboard.c -- it is replaced by the settings in Config.lb, and the support in cs5536.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/devices/pci_device.c')
-rw-r--r--src/devices/pci_device.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index f89f5bbbda..9451ea35aa 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -1161,7 +1161,7 @@ unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
Tell the EISA int controller this int must be level triggered
THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
*/
-static void pci_level_irq(unsigned char intNum)
+void pci_level_irq(unsigned char intNum)
{
unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);