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| author | Dan Lykowski <lykowdk@gmail.com> | 2009-02-05 02:18:42 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2009-02-05 02:18:42 +0000 |
| commit | 4505948faec7cc30edb9daebf53ca006d4a1645a (patch) | |
| tree | 25df2a2bfd49a6c61f6e27ddf686266e2804dc20 /src/devices/pci_rom.c | |
| parent | 8db0cfefd16c9aa6dbc0ffdfd9d2ba81a1561650 (diff) | |
| download | coreboot-4505948faec7cc30edb9daebf53ca006d4a1645a.tar.xz | |
Use the correct device for switching on HDA.
Reorder HDA (HD Audio) init:
The reordering was based on what order things happen in the BIOS
Developers guide, RPR, and SATA driver. I fixed the order of the devices
that didn't matter to clean up the change log.
1. Enable the Chip
2. Setup the SMBus registers
3. Setup the Device Registers
4. Look for Codec
5. Init Codec
The codec init was changed to match the description in the RRG pg 235.
Mem Reg: Base + 08h Bit 0. There were unneeded things happening.
Added 1ms delay to match the BKDG while waiting for BAR+0xe to set its
bits.
Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
Tested on AMD DBM690T and AMD Pistachio by Maggie Li. Works.
Tested on Asus M2A-VM by Carl-Daniel Hailfinger. Improves the situation,
but some warnings remain.
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/devices/pci_rom.c')
0 files changed, 0 insertions, 0 deletions