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authorMarc Jones <marc.jones@amd.com>2007-09-26 16:41:15 +0000
committerMarc Jones <marc.jones@amd.com>2007-09-26 16:41:15 +0000
commit03f23221750754de1975764a19efece231185866 (patch)
tree98f638541b03b3e6a35d11fef2e6acd1a58d6576 /src/devices
parentc3da36681de646b7581a87d3e461f973797db92d (diff)
downloadcoreboot-03f23221750754de1975764a19efece231185866.tar.xz
Don't arbitrarily enable PERR# and SERR# for PCI devices.
It is platform specific. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/devices')
-rw-r--r--src/devices/pci_device.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 7264112806..3d98ee5082 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -603,7 +603,6 @@ void pci_dev_enable_resources(struct device *dev)
}
command = pci_read_config16(dev, PCI_COMMAND);
command |= dev->command;
- command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); /* error check */
printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
pci_write_config16(dev, PCI_COMMAND, command);
}