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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-15 21:37:48 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-12-20 18:14:34 +0000
commit520717dff196e1d1ed61f72a8abadbc114ee6ba1 (patch)
tree5658d5fb27c6f5901c9b714fd1c6839ed36e28f9 /src/drivers/amd/agesa/bootblock.c
parentb9bd69e70ed355d89ff41d66ed7134338c5986fe (diff)
downloadcoreboot-520717dff196e1d1ed61f72a8abadbc114ee6ba1.tar.xz
AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK
Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37440 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/amd/agesa/bootblock.c')
-rw-r--r--src/drivers/amd/agesa/bootblock.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c
index 91fcc6b994..7732f27fd5 100644
--- a/src/drivers/amd/agesa/bootblock.c
+++ b/src/drivers/amd/agesa/bootblock.c
@@ -16,6 +16,7 @@
#include <timestamp.h>
#include <amdblocks/amd_pci_mmconf.h>
#include <amdblocks/biosram.h>
+#include <arch/bootblock.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic.h>
@@ -29,6 +30,11 @@ static void set_early_mtrrs(void)
OPTIMAL_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
}
+void bootblock_soc_early_init(void)
+{
+ bootblock_early_southbridge_init();
+}
+
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
enable_pci_mmconf();