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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-07 22:13:10 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-27 10:39:20 +0000 |
commit | 56397364c9178cae527520a5fffb9eab2f6cc35b (patch) | |
tree | 6eef7e601f8e7c07c0e8f6f59caa776ade7af06f /src/drivers/amd/agesa/cache_as_ram.S | |
parent | 46f04cbb49fbab5854d395edefea5b5f81df572e (diff) | |
download | coreboot-56397364c9178cae527520a5fffb9eab2f6cc35b.tar.xz |
binaryPI: Drop CAR teardown without POSTCAR_STAGE
The remaining (active) binaryPI boards moved away from
BINARYPI_LEGACY_WRAPPER and have POSTCAR_STAGE now.
As the cache_as_ram.S is also used with AGESA, this slightly
reduces the codesize there for romstage and postcar as well.
This commit is actually a revert for the vendorcode parts,
AMD originally shipped the codes using 'invd' for the CAR
teardown, but these were changed for coreboot due the
convoluted teardown that used to happen with non-empty stack.
Change-Id: I693c104c3aab3be537c00695cbd764a48bd603b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/18526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/amd/agesa/cache_as_ram.S')
-rw-r--r-- | src/drivers/amd/agesa/cache_as_ram.S | 58 |
1 files changed, 1 insertions, 57 deletions
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index dcb0c43d8e..3f1358a2f8 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -27,7 +27,6 @@ .code32 .globl _cache_as_ram_setup, _cache_as_ram_setup_end -.globl chipset_teardown_car _cache_as_ram_setup: @@ -105,66 +104,11 @@ _cache_as_ram_setup: pushl %eax call romstage_main -#if CONFIG(POSTCAR_STAGE) - -/* We do not return. Execution continues with run_postcar_phase() - * calling to chipset_teardown_car below. - */ - jmp postcar_entry_failure - -chipset_teardown_car: - -/* - * Retrieve return address from stack as it will get trashed below if - * execution is utilizing the cache-as-ram stack. - */ - pop %esp - -#else - - movl %eax, %esp - -/* Register %esp is new stacktop for remaining of romstage. */ - -#endif - - /* Disable cache */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - -/* Register %esp is preserved in AMD_DISABLE_STACK. */ - AMD_DISABLE_STACK - -#if CONFIG(POSTCAR_STAGE) - - jmp *%esp - -#else - - /* enable cache */ - movl %cr0, %eax - andl $0x9fffffff, %eax - movl %eax, %cr0 - - call romstage_after_car - -#endif - /* Should never see this postcode */ - post_code(0xaf) + post_code(0xae) stop: hlt jmp stop -/* These are here for linking purposes. */ -.weak early_all_cores, romstage_main -early_all_cores: -romstage_main: -postcar_entry_failure: - /* Should never see this postcode */ - post_code(0xae) - jmp stop - _cache_as_ram_setup_end: |