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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-12-26 14:12:38 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-12-26 14:12:38 +0000 |
| commit | 2d1d9cebffbd48d2c3737ff8c919da76e5f12586 (patch) | |
| tree | ee03ad0ffefb5b883867c5784e042fd2cd98d005 /src/drivers/dec/21143 | |
| parent | 19d69e3bab787f51f2eb9bef48bc49468a635016 (diff) | |
| download | coreboot-2d1d9cebffbd48d2c3737ff8c919da76e5f12586.tar.xz | |
Random fixes for TI pci1x2x / Nokia IP530 / others.
- nokia/ip530/devicetree.cb, southbridge/ti/pci1x2x/pci1x2x.c:
- Fix SMSC FDC37B787 name (was a typo).
- Disable PS/2 keyboard/mouse LDN, the IP530 doesn't have either.
- Fix typo: s/PCI_DEVICE_ID_TI_1420/PCI_DEVICE_ID_TI_1520/.
- All of these are confirmed by Marc Bertens on IRC.
- Fix a few CHIP_NAME HP board names.
- Random whitespace and coding-style fixes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/drivers/dec/21143')
| -rw-r--r-- | src/drivers/dec/21143/21143.c | 51 |
1 files changed, 29 insertions, 22 deletions
diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c index 62567c8038..7ca6f12078 100644 --- a/src/drivers/dec/21143/21143.c +++ b/src/drivers/dec/21143/21143.c @@ -38,33 +38,40 @@ /* CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION try 0x02800107 or 0x02800007 if unsure */ /** - * This driver take the values from Kconfig and load them in the registers + * This driver takes the values from Kconfig and loads them in the registers. */ -static void dec_21143_enable( device_t dev ) +static void dec_21143_enable(device_t dev) { - printk( BIOS_DEBUG, "Init of DECchip 21143 Kconfig style\n"); - // Command and Status Configuration Register (Offset 0x04) - pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION ); - printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) ); - // Cache Line Size Register (Offset 0x0C) - pci_write_config8( dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE ); - printk( BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", pci_read_config32(dev, 0x0C) ); - // Expansion ROM Base Address Register (Offset 0x30) - pci_write_config32( dev, 0x30, CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS ); - printk( BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", pci_read_config32(dev, 0x30) ); - return; + printk(BIOS_DEBUG, "Initializing DECchip 21143\n"); + + /* Command and status configuration (offset 0x04) */ + pci_write_config32(dev, 0x04, + CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION); + printk(BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", + pci_read_config32(dev, 0x04)); + + /* Cache line size (offset 0x0C) */ + pci_write_config8(dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE); + printk(BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", + pci_read_config32(dev, 0x0C)); + + /* Expansion ROM base address (offset 0x30) */ + pci_write_config32(dev, 0x30, + CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS); + printk(BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", + pci_read_config32(dev, 0x30)); } -static struct device_operations dec_21143_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = dec_21143_enable, - .scan_bus = 0, +static struct device_operations dec_21143_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = dec_21143_enable, + .scan_bus = 0, }; static const struct pci_driver dec_21143_driver __pci_driver = { - .ops = &dec_21143_ops, - .vendor = PCI_VENDOR_ID_DEC, - .device = PCI_DEVICE_ID_DEC_21142, + .ops = &dec_21143_ops, + .vendor = PCI_VENDOR_ID_DEC, + .device = PCI_DEVICE_ID_DEC_21142, }; |