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author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2018-09-25 10:13:47 +0200 |
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committer | Werner Zeh <werner.zeh@siemens.com> | 2018-09-27 15:55:46 +0000 |
commit | 7e15e87eccf8adbfdeb22dd1bca98d977c99bde1 (patch) | |
tree | 8b59921cb157342d763b870cf41b45d5ef7950b4 /src/drivers/generic/bayhub/bh720.c | |
parent | 899e2ce6ce36ab9c1a67dd480777e5c07b29951e (diff) | |
download | coreboot-7e15e87eccf8adbfdeb22dd1bca98d977c99bde1.tar.xz |
siemens/mc_apl1: Make the DDR memory swizzle data configurable
In preparation for a future MC Apollo Lake board which will be equipped
with LPDDR4 modules, it is necessary to make the swizzle data
configurable. Starting from the mc_apl1 baseboard, which is equipped
with DDR3L memory and therefore does not need swizzle data, the
structures are initialized with zero.
Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/drivers/generic/bayhub/bh720.c')
0 files changed, 0 insertions, 0 deletions