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authorRaul E Rangel <rrangel@chromium.org>2020-05-11 16:26:35 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-05-13 08:36:46 +0000
commit789aefc2272c2ffb3ca2c9380ccdc1a2288f2534 (patch)
treed7d68ddda073989308477c304d58a15439ca3ac8 /src/drivers/i2c
parent658a2913a5bbe9c638c0d069ea663ecb77b490b0 (diff)
downloadcoreboot-789aefc2272c2ffb3ca2c9380ccdc1a2288f2534.tar.xz
soc/amd/picasso: Mark FCH MMIO addresses as non-posted
Immediately following FSP-S, update the data fabric routing registers to make the region between HPET and LAPIC as non-posted. If AGESA is modified to do this, we can delete data_fabric_util.c. If AGESA is modified to not program the registers, then we can simplify data_fabric_set_mmio_np(). BUG=b:147042464, b:156296146 TEST=boot trembyle Change-Id: Idbafaac158f5a4c533d2d88db79bb4d6244e5355 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41268 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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