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authorTim Wawrzynczak <twawrzynczak@chromium.org>2020-05-29 14:29:53 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-07-07 17:22:46 +0000
commit46f6fcf88f2db397759f69d0c7ddf11d88b61e03 (patch)
treec520011ec212b4fae6522f4f49b0f5149c10c15b /src/drivers/intel/dptf/dptf.c
parent3a9cde9ab630fa34240b16f7e6ae10b5a61aa67e (diff)
downloadcoreboot-46f6fcf88f2db397759f69d0c7ddf11d88b61e03.tar.xz
dptf: Add support for Charger Performance States
This change generates the DPTF TCHG.PPSS table in the SSDT. This table describes different charging rates which are available to use. DPTF can pick different rates in order to passively cool (or not) the system. BUG=b:143539650 TEST=compiles Change-Id: I6df6bfbac628fa4e4d313e38b8e6c53fce70a7f2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/drivers/intel/dptf/dptf.c')
-rw-r--r--src/drivers/intel/dptf/dptf.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c
index 5cad07dade..a20087fff3 100644
--- a/src/drivers/intel/dptf/dptf.c
+++ b/src/drivers/intel/dptf/dptf.c
@@ -72,6 +72,9 @@ static void dptf_fill_ssdt(const struct device *dev)
dptf_write_critical_policies(config->policies.critical,
DPTF_MAX_CRITICAL_POLICIES);
+ /* Controls */
+ dptf_write_charger_perf(config->controls.charger_perf, DPTF_MAX_CHARGER_PERF_STATES);
+
printk(BIOS_INFO, "\\_SB.DPTF: %s at %s\n", dev->chip_ops->name, dev_path(dev));
}