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authorNico Huber <nico.h@gmx.de>2018-05-26 17:47:42 +0200
committerNico Huber <nico.h@gmx.de>2018-05-31 15:08:48 +0000
commitb4953a93aa855afcf801d6f7d48df18f31ee2598 (patch)
tree169121e3fe449dca2a8707c510cf44434df9f28b /src/drivers/intel/fsp1_0
parentc51df93ccfefb1a5d1dd763d5b8f400c928593a0 (diff)
downloadcoreboot-b4953a93aa855afcf801d6f7d48df18f31ee2598.tar.xz
cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE
As far as I can see this Kconfig option was used wrong ever since it was added. According to the commit message of 107f72e (Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary to prevent overlapping with CAR. Let's handle the potential overlap in C macros instead and get rid of that option. Currently, it was only used by most FSP1.0 boards, and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?). Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel/fsp1_0')
-rw-r--r--src/drivers/intel/fsp1_0/Kconfig9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig
index 6aa89491e4..c7f6c18f86 100644
--- a/src/drivers/intel/fsp1_0/Kconfig
+++ b/src/drivers/intel/fsp1_0/Kconfig
@@ -103,15 +103,6 @@ config VIRTUAL_ROM_SIZE
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
size is 16 MB.
-config CACHE_ROM_SIZE_OVERRIDE
- hex "Cache ROM Size"
- default CBFS_SIZE
- help
- This is the size of the cachable area that is passed into the FSP in
- the early initialization. Typically this should be the size of the CBFS
- area, but the size must be a power of 2 whereas the CBFS size does not
- have this limitation.
-
config USE_GENERIC_FSP_CAR_INC
bool
default n