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| author | Duncan Laurie <dlaurie@chromium.org> | 2015-11-22 14:53:57 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-12-03 14:17:51 +0100 |
| commit | fb509830085e379cee8eb9b5f619c34c249c9d77 (patch) | |
| tree | 6ef8091fb064c4485267082995ac858ee28cc477 /src/drivers/intel/fsp1_0 | |
| parent | 590ac64d5571d8b85e0ddd65b25b8cda9354de15 (diff) | |
| download | coreboot-fb509830085e379cee8eb9b5f619c34c249c9d77.tar.xz | |
intel/fsp: Add post codes for FSP phases
Add post codes for the various FSP phases and use them as appropriate
in FSP 1.0 and 1.1 implementations.
This will make it more consistent to debug FSP hangs and resets.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados and chell
Change-Id: I32f8dde80a0c6c117fe0fa48cdfe2f9a83b9dbdf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3b616ff3c9d8b6d05c8bfe7f456f5c189e523547
Original-Change-Id: I081745dcc45b3e9e066ade2227e675801d6f669a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313822
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12595
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/drivers/intel/fsp1_0')
| -rw-r--r-- | src/drivers/intel/fsp1_0/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_0/fsp_util.c | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc index 24de3a8084..045bfb31bc 100644 --- a/src/drivers/intel/fsp1_0/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc @@ -47,7 +47,7 @@ find_fsp_ret: jmp .Lhlt find_fsp_ok: - post_code(0x22) + post_code(POST_FSP_TEMP_RAM_INIT) /* Calculate entry into FSP */ mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index ca381ff7ae..8688ca54ff 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -92,6 +92,7 @@ void __attribute__ ((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr) /* Call back to romstage for board specific changes */ romstage_fsp_rt_buffer_callback(&FspRtBuffer); + post_code(POST_FSP_MEMORY_INIT); FspInitApi(&FspInitParams); /* Should never return. Control will continue from ContinuationFunc */ @@ -321,6 +322,7 @@ static void fsp_after_pci_enum(void *unused) { /* This call needs to be done before resource allocation. */ printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); + post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE); FspNotify(EnumInitPhaseAfterPciEnumeration); printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); @@ -334,6 +336,7 @@ static void fsp_finalize(void *unused) { printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n"); print_fsp_info(); + post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE); FspNotify(EnumInitPhaseReadyToBoot); printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n"); } |