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author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-04-20 15:29:16 -0700 |
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committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-05-23 01:33:31 +0200 |
commit | b5ad827ee584a960212ae983e30cd1a0b18c55a5 (patch) | |
tree | 915ca1f01080073fe24007c0903bf04c33378699 /src/drivers/intel/fsp1_1/Makefile.inc | |
parent | 65ff63f5ea70ca08d451d8e25791bf1200ce8c11 (diff) | |
download | coreboot-b5ad827ee584a960212ae983e30cd1a0b18c55a5.tar.xz |
drivers/intel: Update FSP 1.1 Driver
Update the FSP driver files from 1.0 to 1.1.
Updates will occur manually to these files only for FSP 1.1 support. An
fsp_x_y should be added in the future to support newer versions of the
FSP specification.
Please note that due to the interface with EDK2, these files make
references to data structures and fields that use CamelCase.
BRANCH=none
BUG=None
TEST=Build for Braswell or Skylake boards using FSP 1.1.
Change-Id: I2914c047d786a3060075356783ac9758bc41f633
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10049
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/drivers/intel/fsp1_1/Makefile.inc')
-rw-r--r-- | src/drivers/intel/fsp1_1/Makefile.inc | 34 |
1 files changed, 24 insertions, 10 deletions
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index a29bf32136..9bb3fc4842 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2014 Sage Electronic Engineering, LLC. +# Copyright (C) 2015 Intel Corp. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,18 +18,29 @@ # Foundation, Inc. # -ramstage-y += fsp_util.c hob.c -romstage-y += fsp_util.c hob.c +romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c +romstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c +romstage-y += fsp_util.c +romstage-y += hob.c ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c -romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c +ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c +ramstage-y += fsp_relocate.c +ramstage-y += fsp_util.c +ramstage-y += hob.c -CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 +CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1 + +cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc -ifeq ($(CONFIG_USE_GENERIC_FSP_CAR_INC),y) -cpu_incs += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc -endif +# Add the GOP Video BIOS Table to the cbfs image +cbfs-files-$(CONFIG_GOP_SUPPORT) += vbt.bin +vbt.bin-file := $(call strip_quotes,$(CONFIG_VBT_FILE)) +vbt.bin-type := optionrom + + +# Add the FSP binary to the cbfs image ifeq ($(CONFIG_HAVE_FSP_BIN),y) cbfs-files-y += fsp.bin fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) @@ -36,14 +48,16 @@ fsp.bin-position := $(CONFIG_FSP_LOC) fsp.bin-type := fsp endif -ifeq ($(CONFIG_ENABLE_MRC_CACHE),y) + +# Create and add the MRC cache to the cbfs image +ifeq ($(CONFIG_ENABLE_MRC_CACHE_FILE),y) $(obj)/mrc.cache: dd if=/dev/zero count=1 \ bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \ tr '\000' '\377' > $@ cbfs-files-y += mrc.cache -mrc.cache-file := $(obj)/mrc.cache +mrc.cache-file := $(call strip_quotes,$(CONFIG_MRC_CACHE_FILE)) mrc.cache-position := $(CONFIG_MRC_CACHE_LOC) -mrc.cache-type := mrc_cache +mrc.cache-type := CBFS_TYPE_MRC_CACHE endif |