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| author | Aaron Durbin <adurbin@chromium.org> | 2015-08-27 22:49:03 -0500 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-08-29 01:51:48 +0000 |
| commit | 80f5d5b3e4aedf456b60b976fe3419471dcad609 (patch) | |
| tree | 7c5f817ed19209c272627a9c199b99d09d77eebd /src/drivers/intel/fsp1_1/fsp_util.h | |
| parent | bc140cf1114ba08966f8940e1047f7ee4c35da75 (diff) | |
| download | coreboot-80f5d5b3e4aedf456b60b976fe3419471dcad609.tar.xz | |
fsp1_1: remove duplicate mrc caching mechanism
For some reason fsp 1.1 has a duplicate mechanism for saving
mrc data as soc/intel/common. Defer to the common code as all
the existing users were already using the common code.
BUG=chrome-os-partner:44620
BRANCH=None
TEST=Built and booted glados. Suspended and resumed.
Change-Id: I951d47deb85445a5f010d23dfd11abb0b6f65e5e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Original-Commit-Id: 2138b6ff1517c440d24f72a5f399bd6cb6097274
Original-Change-Id: I06609c1435b06b1365b1762f83cfcba532eb8c7a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295236
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11454
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/drivers/intel/fsp1_1/fsp_util.h')
| -rw-r--r-- | src/drivers/intel/fsp1_1/fsp_util.h | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/src/drivers/intel/fsp1_1/fsp_util.h b/src/drivers/intel/fsp1_1/fsp_util.h index fba91165a1..8f6f77a6e7 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.h +++ b/src/drivers/intel/fsp1_1/fsp_util.h @@ -41,11 +41,6 @@ /* Include the EDK2 headers */ #include <soc/chipset_fsp_util.h> -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) -int save_mrc_data(void *hob_start); -void * find_and_set_fastboot_cache(void); -#endif - /* find_fsp() should only be called from assembly code. */ FSP_INFO_HEADER *find_fsp(void); /* Set FSP's runtime information. */ @@ -86,23 +81,6 @@ int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src); #define EFI_HOB_TYPE_HANDOFF 0x0001 #define EFI_HOB_TYPE_MEMORY_POOL 0x0007 -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - -struct mrc_data_container *find_current_mrc_cache(void); -void update_mrc_cache(void *unused); - -#endif /* CONFIG_ENABLE_MRC_CACHE */ - /* The offset in bytes from the start of the info structure */ #define FSP_IMAGE_SIG_LOC 0 #define FSP_IMAGE_ID_LOC 16 |