diff options
| author | Frans Hendriks <fhendriks@eltan.com> | 2018-11-19 11:59:00 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-22 15:02:23 +0000 |
| commit | 613da18fecc757ed75dca97578f316b15bd3f826 (patch) | |
| tree | b35391ef83d87822201feedac1abb0cb33cb3d51 /src/drivers/intel/fsp1_1 | |
| parent | 166cbdec5b042f28badedd09da1203c9a1feccfc (diff) | |
| download | coreboot-613da18fecc757ed75dca97578f316b15bd3f826.tar.xz | |
drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S
soc/car_setup.S is included when SKIP_FSP_CAR is enabled,
but no chipset/SoC have car_setup.S available.
Remove include and post_code() call always solving build errors.
BUG=NA
TEST=NA
Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
Diffstat (limited to 'src/drivers/intel/fsp1_1')
| -rw-r--r-- | src/drivers/intel/fsp1_1/cache_as_ram.inc | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index af6f3a91e1..934ae670dc 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -37,19 +37,6 @@ cache_as_ram: post_code(0x20) -#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) - - /* - * SOC specific setup - * NOTE: This has to preserve the registers - * mm0, mm1 and edi. - */ - #include <soc/car_setup.S> - - post_code(0x28) - -#endif - /* * Find the FSP binary in cbfs. * Make a fake stack that has the return value back to this code. |