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authorAaron Durbin <adurbin@chromium.org>2018-04-21 14:45:32 -0600
committerAaron Durbin <adurbin@chromium.org>2018-04-24 14:37:59 +0000
commit6403167d290da235a732bd2d6157aa2124fb403a (patch)
tree9c4805af37a31830934f91098d299e967df930c6 /src/drivers/intel/fsp1_1
parent38fd6685e9da61daadc96a8d537e6966dfe3b219 (diff)
downloadcoreboot-6403167d290da235a732bd2d6157aa2124fb403a.tar.xz
compiler.h: add __weak macro
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1')
-rw-r--r--src/drivers/intel/fsp1_1/car.c9
-rw-r--r--src/drivers/intel/fsp1_1/raminit.c7
-rw-r--r--src/drivers/intel/fsp1_1/ramstage.c9
-rw-r--r--src/drivers/intel/fsp1_1/romstage.c23
4 files changed, 26 insertions, 22 deletions
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index e1a9b9db6c..686a4c8c7e 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -14,6 +14,7 @@
*/
#include <arch/early_variables.h>
+#include <compiler.h>
#include <console/console.h>
#include <fsp/car.h>
#include <fsp/util.h>
@@ -100,18 +101,18 @@ asmlinkage void after_cache_as_ram(void *chipset_context)
after_cache_as_ram_stage();
}
-void __attribute__((weak)) car_mainboard_pre_console_init(void)
+void __weak car_mainboard_pre_console_init(void)
{
}
-void __attribute__((weak)) car_soc_pre_console_init(void)
+void __weak car_soc_pre_console_init(void)
{
}
-void __attribute__((weak)) car_mainboard_post_console_init(void)
+void __weak car_mainboard_post_console_init(void)
{
}
-void __attribute__((weak)) car_soc_post_console_init(void)
+void __weak car_soc_post_console_init(void)
{
}
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 2bdac0a340..e5714ae140 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -15,6 +15,7 @@
#include <arch/acpi.h>
#include <cbmem.h>
+#include <compiler.h>
#include <console/console.h>
#include <fsp/memmap.h>
#include <fsp/romstage.h>
@@ -296,7 +297,7 @@ void raminit(struct romstage_params *params)
}
/* Initialize the UPD parameters for MemoryInit */
-__attribute__((weak)) void mainboard_memory_init_params(
+__weak void mainboard_memory_init_params(
struct romstage_params *params,
MEMORY_INIT_UPD *upd_ptr)
{
@@ -304,7 +305,7 @@ __attribute__((weak)) void mainboard_memory_init_params(
}
/* Display the UPD parameters for MemoryInit */
-__attribute__((weak)) void soc_display_memory_init_params(
+__weak void soc_display_memory_init_params(
const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new)
{
printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
@@ -312,7 +313,7 @@ __attribute__((weak)) void soc_display_memory_init_params(
}
/* Initialize the UPD parameters for MemoryInit */
-__attribute__((weak)) void soc_memory_init_params(
+__weak void soc_memory_init_params(
struct romstage_params *params,
MEMORY_INIT_UPD *upd)
{
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index 563a030220..a4609df573 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -18,6 +18,7 @@
#include <arch/acpi.h>
#include <cbmem.h>
#include <cbfs.h>
+#include <compiler.h>
#include <console/console.h>
#include <fsp/memmap.h>
#include <fsp/ramstage.h>
@@ -28,7 +29,7 @@
#include <timestamp.h>
/* SOC initialization after FSP silicon init */
-__attribute__((weak)) void soc_after_silicon_init(void)
+__weak void soc_after_silicon_init(void)
{
}
@@ -215,13 +216,13 @@ void intel_silicon_init(void)
}
/* Initialize the UPD parameters for SiliconInit */
-__attribute__((weak)) void mainboard_silicon_init_params(
+__weak void mainboard_silicon_init_params(
SILICON_INIT_UPD *params)
{
};
/* Display the UPD parameters for SiliconInit */
-__attribute__((weak)) void soc_display_silicon_init_params(
+__weak void soc_display_silicon_init_params(
const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new)
{
printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
@@ -229,6 +230,6 @@ __attribute__((weak)) void soc_display_silicon_init_params(
}
/* Initialize the UPD parameters for SiliconInit */
-__attribute__((weak)) void soc_silicon_init_params(SILICON_INIT_UPD *params)
+__weak void soc_silicon_init_params(SILICON_INIT_UPD *params)
{
}
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 88401f0b4b..ba08cdc42b 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -20,6 +20,7 @@
#include <arch/cbfs.h>
#include <arch/early_variables.h>
#include <assert.h>
+#include <compiler.h>
#include <console/console.h>
#include <cbmem.h>
#include <cpu/intel/microcode.h>
@@ -185,13 +186,13 @@ void after_cache_as_ram_stage(void)
}
/* Initialize the power state */
-__attribute__((weak)) struct chipset_power_state *fill_power_state(void)
+__weak struct chipset_power_state *fill_power_state(void)
{
return NULL;
}
/* Board initialization before and after RAM is enabled */
-__attribute__((weak)) void mainboard_romstage_entry(
+__weak void mainboard_romstage_entry(
struct romstage_params *params)
{
post_code(0x31);
@@ -201,7 +202,7 @@ __attribute__((weak)) void mainboard_romstage_entry(
}
/* Save the DIMM information for SMBIOS table 17 */
-__attribute__((weak)) void mainboard_save_dimm_info(
+__weak void mainboard_save_dimm_info(
struct romstage_params *params)
{
int channel;
@@ -330,7 +331,7 @@ __attribute__((weak)) void mainboard_save_dimm_info(
}
/* Add any mainboard specific information */
-__attribute__((weak)) void mainboard_add_dimm_info(
+__weak void mainboard_add_dimm_info(
struct romstage_params *params,
struct memory_info *mem_info,
int channel, int dimm, int index)
@@ -338,44 +339,44 @@ __attribute__((weak)) void mainboard_add_dimm_info(
}
/* Get the memory configuration data */
-__attribute__((weak)) int mrc_cache_get_current(int type, uint32_t version,
+__weak int mrc_cache_get_current(int type, uint32_t version,
struct region_device *rdev)
{
return -1;
}
/* Save the memory configuration data */
-__attribute__((weak)) int mrc_cache_stash_data(int type, uint32_t version,
+__weak int mrc_cache_stash_data(int type, uint32_t version,
const void *data, size_t size)
{
return -1;
}
/* Transition RAM from off or self-refresh to active */
-__attribute__((weak)) void raminit(struct romstage_params *params)
+__weak void raminit(struct romstage_params *params)
{
post_code(0x34);
die("ERROR - No RAM initialization specified!\n");
}
/* Display the memory configuration */
-__attribute__((weak)) void report_memory_config(void)
+__weak void report_memory_config(void)
{
}
/* Choose top of stack and setup MTRRs */
-__attribute__((weak)) void *setup_stack_and_mtrrs(void)
+__weak void *setup_stack_and_mtrrs(void)
{
die("ERROR - Must specify top of stack!\n");
return NULL;
}
/* SOC initialization after RAM is enabled */
-__attribute__((weak)) void soc_after_ram_init(struct romstage_params *params)
+__weak void soc_after_ram_init(struct romstage_params *params)
{
}
/* SOC initialization before RAM is enabled */
-__attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params)
+__weak void soc_pre_ram_init(struct romstage_params *params)
{
}