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authorJulius Werner <jwerner@chromium.org>2017-12-05 13:39:10 -0800
committerJulius Werner <jwerner@chromium.org>2017-12-07 01:18:25 +0000
commite2f17f782f6a9236259f2c25ac30d35dc24d45bb (patch)
tree6c788bd8c2543c94abffa298952d974b38c2d0b2 /src/drivers/intel/fsp1_1
parentec477346bfe8f73aac225e9a8c2c5e6438bba593 (diff)
downloadcoreboot-e2f17f782f6a9236259f2c25ac30d35dc24d45bb.tar.xz
boardid: Minor clean up and standardization
Merge the different coreboot table strapping ID structures into one because they're really just all the same, and I want to add more. Make the signature of the board_id() function return a uint32_t because that's also what goes in the coreboot table. Add a printk to the generic code handling strapping IDs in ramstage so that not every individual mainboard implementation needs its own print. (In turn, remove one such print from fsp1_1 code because it's in the way of my next patch.) Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1')
-rw-r--r--src/drivers/intel/fsp1_1/romstage.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index d79bc2f8c0..e6dec251be 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -20,7 +20,6 @@
#include <arch/cbfs.h>
#include <arch/early_variables.h>
#include <assert.h>
-#include <boardid.h>
#include <console/console.h>
#include <cbmem.h>
#include <cpu/intel/microcode.h>
@@ -74,13 +73,6 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
/* Get power state */
params.power_state = fill_power_state();
- /*
- * Read and print board version. Done after SOC romstage
- * in case PCH needs to be configured to talk to the EC.
- */
- if (IS_ENABLED(CONFIG_BOARD_ID_AUTO))
- printk(BIOS_INFO, "MLB: board version %d\n", board_id());
-
/* Call into mainboard. */
mainboard_romstage_entry(&params);
soc_after_ram_init(&params);