diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-12-08 17:00:23 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-12-10 04:43:58 +0100 |
| commit | 6d720f38e06d14cc8a89635f66dc124dcd5ac150 (patch) | |
| tree | 874aecaf8f35d8db1740dabc7735e3e44cb9ca5e /src/drivers/intel/fsp1_1 | |
| parent | bf3dbaf86d033becc231a48612d474fac9add1ee (diff) | |
| download | coreboot-6d720f38e06d14cc8a89635f66dc124dcd5ac150.tar.xz | |
cbfs/vboot: remove firmware component support
The Chrome OS verified boot path supported multiple CBFS
instances in the boot media as well as stand-alone assets
sitting in each vboot RW slot. Remove the support for the
stand-alone assets and always use CBFS accesses as the
way to retrieve data.
This is implemented by adding a cbfs_locator object which
is queried for locating the current CBFS. Additionally, it
is also signalled prior to when a program is about to be
loaded by coreboot for the subsequent stage/payload. This
provides the same opportunity as previous for vboot to
hook in and perform its logic.
BUG=chromium:445938
BRANCH=None
TEST=Built and ran on glados.
CQ-DEPEND=CL:307121,CL:31691,CL:31690
Change-Id: I6a3a15feb6edd355d6ec252c36b6f7885b383099
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12689
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1')
| -rw-r--r-- | src/drivers/intel/fsp1_1/car.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 9d71faa733..23312e14cc 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -14,11 +14,11 @@ */ #include <arch/early_variables.h> -#include <assets.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include <fsp/car.h> #include <fsp/util.h> +#include <program_loading.h> #include <soc/intel/common/util.h> #include <timestamp.h> @@ -79,15 +79,17 @@ asmlinkage void *romstage_after_verstage(void) /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram * is still enabled. We can directly access work buffer here. */ FSP_INFO_HEADER *fih; - struct asset fsp = ASSET_INIT(ASSET_REFCODE, "fsp.bin"); + struct prog fsp = PROG_INIT(ASSET_REFCODE, "fsp.bin"); console_init(); - if (asset_locate(&fsp)) { + if (prog_locate(&fsp)) { fih = NULL; - printk(BIOS_ERR, "Unable to locate %s\n", asset_name(&fsp)); + printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp)); } else - fih = find_fsp((uintptr_t)asset_mmap(&fsp)); + /* This leaks a mapping which this code assumes is benign as + * the flash is memory mapped CPU's address space. */ + fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); set_fih_car(fih); |