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author | Aaron Durbin <adurbin@chromium.org> | 2017-12-15 12:26:40 -0700 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2017-12-17 18:29:41 +0000 |
commit | decd062875c1e33d4c9203c2edc0652792a46e73 (patch) | |
tree | 83da2b2b82f3e0b5298f89ed2477637ec0766a16 /src/drivers/intel/fsp1_1 | |
parent | 934f433d87df0440294be6fc2e6395e0139a5e34 (diff) | |
download | coreboot-decd062875c1e33d4c9203c2edc0652792a46e73.tar.xz |
drivers/mrc_cache: move mrc_cache support to drivers
There's nothing intel-specific about the current mrc_cache support.
It's logic manages saving non-volatile areas into the boot media.
Therefore, expose it to the rest of the system for any and all to
use.
BUG=b:69614064
Change-Id: I3b331c82a102f88912a3e10507a70207fb20aecc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/drivers/intel/fsp1_1')
-rw-r--r-- | src/drivers/intel/fsp1_1/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index e6dec251be..81939c4c33 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -28,11 +28,11 @@ #include <ec/google/chromeec/ec_commands.h> #include <elog.h> #include <fsp/romstage.h> +#include <mrc_cache.h> #include <reset.h> #include <program_loading.h> #include <romstage_handoff.h> #include <smbios.h> -#include <soc/intel/common/mrc_cache.h> #include <stage_cache.h> #include <string.h> #include <timestamp.h> |