diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-02-20 13:33:32 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-02-22 00:40:32 +0100 |
| commit | f4b20af9d716ff57d78d5d576e2990903bd70842 (patch) | |
| tree | 69603260f4c95fbbcab75a6333e23068fda2dc18 /src/drivers/intel/fsp1_1 | |
| parent | 39bfc6cb136e641955ca5db477be43715ac72454 (diff) | |
| download | coreboot-f4b20af9d716ff57d78d5d576e2990903bd70842.tar.xz | |
drivers/intel/{fsp1_1,fsp2_0}: Provide separate function for fsp load
Add a function to allow FSP component loading separately from silicon
initialization. This enables SoCs that might not have stage cache
available during silicon initialization to load/save components from/to
stage cache before it is relocated or destroyed.
BUG=chrome-os-partner:63114
BRANCH=None
TEST=Compiles successfully.
Change-Id: Iae77e20568418c29df9f69bd54aa571e153740c9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18413
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1')
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/ramstage.h | 6 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/ramstage.c | 14 |
2 files changed, 18 insertions, 2 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index 5ce6aa8892..a9f6a8db22 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -21,6 +21,12 @@ #include <soc/intel/common/util.h> #include <stdint.h> +/* + * Load FSP from stage cache or CBFS. This allows SoCs to load FSP separately + * from calling silicon init. It might be required in cases where stage cache is + * no longer available by the point SoC calls into silicon init. + */ +void fsp_load(void); /* Perform Intel silicon init. */ void intel_silicon_init(void); void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup); diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index dd1abbeab7..7d9ff8edf0 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -185,11 +185,15 @@ static int fsp_find_and_relocate(struct prog *fsp) return 0; } -void intel_silicon_init(void) +void fsp_load(void) { + static int load_done; struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); int is_s3_wakeup = acpi_is_wakeup_s3(); + if (load_done) + return; + if (is_s3_wakeup && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { printk(BIOS_DEBUG, "FSP: Loading binary from cache\n"); stage_cache_load_stage(STAGE_REFCODE, &fsp); @@ -201,7 +205,13 @@ void intel_silicon_init(void) /* FSP_INFO_HEADER is set as the program entry. */ fsp_update_fih(prog_entry(&fsp)); - fsp_run_silicon_init(fsp_get_fih(), is_s3_wakeup); + load_done = 1; +} + +void intel_silicon_init(void) +{ + fsp_load(); + fsp_run_silicon_init(fsp_get_fih(), acpi_is_wakeup_s3()); } /* Initialize the UPD parameters for SiliconInit */ |