soc/intel/tigerlake: Implement soc_get_pmc_mux_device()

The ChromeOS EC is adding new entries to its USBC.CONx devices (see later
patch), and it needs to get access to the PMC.MUX device so that its
ACPI path can be retrieved. This provides a weak function to return NULL
for all Intel SoCs except for Tiger Lake, which locates the device if it
is found in the devicetree.

Change-Id: I3fe3ef25e9fac8748142f5b1bd870c9bc70b97ff
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40948
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/drivers/intel/pmc_mux/chip.h b/src/drivers/intel/pmc_mux/chip.h
index dcca2a3ecc..f73a07047f 100644
--- a/src/drivers/intel/pmc_mux/chip.h
+++ b/src/drivers/intel/pmc_mux/chip.h
@@ -3,6 +3,8 @@
 #ifndef __DRIVERS_INTEL_PMC_MUX_H__
 #define __DRIVERS_INTEL_PMC_MUX_H__
 
+extern struct chip_operations drivers_intel_pmc_mux_ops;
+
 struct drivers_intel_pmc_mux_config {
 };