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authorAaron Durbin <adurbin@chromium.org>2015-10-29 10:43:21 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-11-05 17:40:05 +0100
commit2524be4aff63e01637d28d6866fa23a513a3b8b1 (patch)
tree36e1c6d7ed7f95f62b2a4aea0b6a58fb1c69a19c /src/drivers/intel
parent102245fbed0b903e107880cb39a43bd8df757180 (diff)
downloadcoreboot-2524be4aff63e01637d28d6866fa23a513a3b8b1.tar.xz
fsp1_1: pass ROM_SIZE to FSP for cacheable RO region
As vboot verification works on regions outside of CBFS pass the entire ROM_SIZE to FSP for creating a cacheable RO region. Additionally remove the CACHE_ROM_SIZE_OVERRIDE as it doesn't work with non-power of 2 CBFS_SIZE. In practice the entire ROM should be attempted to be cached. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados w/ a 3MiB CBFS_SIZE. Change-Id: I61404c626ab2bcfd039d6eb3c01d9c13a0928446 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 92568c630c48446b1ad9d4f22056f22e0679970c Original-Change-Id: I032e4d615d2b68d3a2e597555eb1b5034a74bf0a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309770 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12260 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/drivers/intel')
-rw-r--r--src/drivers/intel/fsp1_1/Kconfig9
-rw-r--r--src/drivers/intel/fsp1_1/cache_as_ram.inc4
2 files changed, 2 insertions, 11 deletions
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 5936f60065..4ae372746e 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -80,15 +80,6 @@ config FSP_LOC
endif #HAVE_FSP_BIN
-config CACHE_ROM_SIZE_OVERRIDE
- hex "Cache ROM Size"
- default CBFS_SIZE
- help
- This is the size of the cachable area that is passed into the FSP in
- the early initialization. Typically this should be the size of the
- CBFS area, but the size must be a power of 2 whereas the CBFS size
- does not have this limitation.
-
config DISPLAY_FAST_BOOT_DATA
bool "Display fast boot data"
default n
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc
index 1d63376ec5..7d68f3210f 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc
@@ -212,8 +212,8 @@ fake_fsp_stack:
CAR_init_params:
.long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
.long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
- .long 0xFFFFFFFF - CONFIG_CBFS_SIZE + 1 /* Firmware Location */
- .long CONFIG_CBFS_SIZE /* Total Firmware Length */
+ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
+ .long CONFIG_ROM_SIZE /* Total Firmware Length */
CAR_init_stack:
.long CAR_init_done