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| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-07-11 12:33:22 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-21 15:55:40 +0000 |
| commit | 399c022a8c6cba7ad6d75fdf377a690395877611 (patch) | |
| tree | 44a66a2fa6f7065e8c82289495b2df0e5065e972 /src/drivers/intel | |
| parent | 4cfae2f574c93c5640958fefa9f218c19e11399d (diff) | |
| download | coreboot-399c022a8c6cba7ad6d75fdf377a690395877611.tar.xz | |
soc/intel/cannonlake: Add postcar stage support
Initialize postcar frame once finish FSP memoryinit
Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp2_0/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index cdf6146d51..d5709adc31 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -43,6 +43,7 @@ postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c postcar-$(CONFIG_FSP_CAR) += util.c postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c +postcar-y += hand_off_block.c CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include |