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authorLee Leahy <leroy.p.leahy@intel.com>2016-01-05 16:34:58 -0800
committerLeroy P Leahy <leroy.p.leahy@intel.com>2016-01-27 21:33:18 +0100
commita608969ebbc556499a20edbb25c2ef45a7434871 (patch)
tree882f2226f2267c3ae871a46e499f9606b9fc2fe1 /src/drivers/intel
parent4b7a00867aba15f71679d406d140014a03d8e7a0 (diff)
downloadcoreboot-a608969ebbc556499a20edbb25c2ef45a7434871.tar.xz
drivers/intel/fsp1_1: Enable builds without MRC cache
Properly use the CONFIG_CACHE_MRC_SETTINGS value to determine when to cache the MRC settings. TEST=Build and run on Galileo Change-Id: Ibc76b20b9603b1e436a68b71d44ca1ca04db7168 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13437 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/drivers/intel')
-rw-r--r--src/drivers/intel/fsp1_1/romstage.c27
1 files changed, 14 insertions, 13 deletions
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 16db4dfd91..b17927ab09 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -128,8 +128,9 @@ void romstage_common(struct romstage_params *params)
/* Recovery mode does not use MRC cache */
printk(BIOS_DEBUG,
"Recovery mode: not using MRC cache.\n");
- } else if (!mrc_cache_get_current_with_version(&cache,
- params->fsp_version)) {
+ } else if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)
+ && (!mrc_cache_get_current_with_version(&cache,
+ params->fsp_version))) {
/* MRC cache found */
params->pei_data->saved_data_size = cache->size;
params->pei_data->saved_data = &cache->data[0];
@@ -150,16 +151,16 @@ void romstage_common(struct romstage_params *params)
timestamp_add_now(TS_AFTER_INITRAM);
/* Save MRC output */
- printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,
- pei_data->data_to_save_size);
- if (params->pei_data->boot_mode != SLEEP_STATE_S3) {
- if (params->pei_data->data_to_save_size != 0 &&
- params->pei_data->data_to_save != NULL) {
- mrc_cache_stash_data_with_version(
- params->pei_data->data_to_save,
- params->pei_data->data_to_save_size,
- params->fsp_version);
- }
+ if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) {
+ printk(BIOS_DEBUG, "MRC data at %p %d bytes\n",
+ pei_data->data_to_save, pei_data->data_to_save_size);
+ if ((params->pei_data->boot_mode != SLEEP_STATE_S3)
+ && (params->pei_data->data_to_save_size != 0)
+ && (params->pei_data->data_to_save != NULL))
+ mrc_cache_stash_data_with_version(
+ params->pei_data->data_to_save,
+ params->pei_data->data_to_save_size,
+ params->fsp_version);
}
/* Save DIMM information */