diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-07-11 12:33:22 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-15 20:21:22 +0000 |
| commit | 8465a81e81dfb2ed1fc24b9cf053b09d86fa5163 (patch) | |
| tree | ff6a331f40c5887ee583359adb4a643905fc1e45 /src/drivers/intel | |
| parent | e2ef3cf8e3ba130fe7388c905fc06aa3ff8b0506 (diff) | |
| download | coreboot-8465a81e81dfb2ed1fc24b9cf053b09d86fa5163.tar.xz | |
soc/intel/cannonlake: Add postcar stage support
Initialize postcar frame once finish FSP memoryinit
This patch was merged too early and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20534
Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20688
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp2_0/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index cdf6146d51..d5709adc31 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -43,6 +43,7 @@ postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c postcar-$(CONFIG_FSP_CAR) += util.c postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c +postcar-y += hand_off_block.c CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include |