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| author | Aaron Durbin <adurbin@chromium.org> | 2016-04-29 12:43:27 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-05-02 20:06:58 +0200 |
| commit | ddf4fa0cc35e6fc65d347b8c9eb4acbe0cba51b9 (patch) | |
| tree | 4237310820a03c6c22d9fa309f7112fd6334597c /src/drivers/intel | |
| parent | aef586548a2443f40a49f9f1f5d99c522a89480f (diff) | |
| download | coreboot-ddf4fa0cc35e6fc65d347b8c9eb4acbe0cba51b9.tar.xz | |
drivers/intel/fsp1_1: fix linking romstage when SEPARATE_VERSTAGE used
The skylake-based Chromebooks use a separate verstage which runs
just after bootblock and prior to romstage. However, that
config is not enabled for coreboot.org so when
C_ENVIRONMENT_BOOTBLOCK changes were done it wasn't observed
that the Chromebook config failed because 2 _start symbols
were present. Remedy this failure by using the common
car_stage_entry symbol for taking over control flow.
Change-Id: I3f29b90ba8e3786b2106a34e49e6d1f9831dcc7c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14549
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp1_1/romstage_after_verstage.S | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/src/drivers/intel/fsp1_1/romstage_after_verstage.S b/src/drivers/intel/fsp1_1/romstage_after_verstage.S index 739db29971..2a3372f905 100644 --- a/src/drivers/intel/fsp1_1/romstage_after_verstage.S +++ b/src/drivers/intel/fsp1_1/romstage_after_verstage.S @@ -16,18 +16,8 @@ #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ .text -.global _start -_start: - /* This is the romstage entry point when CONFIG_SEPARATE_VERSTAGE - * is used. The stack, descriptors, and gdt are already initialized - * by verstage. However, in order to maintain the semantics of - * CAR_GLOBAL variables we need to clear those to zero. */ - cld - xor %eax, %eax - movl $(_car_global_end), %ecx - movl $(_car_global_start), %edi - sub %edi, %ecx - rep stosl +.global car_stage_entry +car_stage_entry: call romstage_after_verstage #include "after_raminit.S" |