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authorKarthikeyan Ramasubramanian <kramasub@chromium.org>2019-05-01 10:22:22 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-05-06 10:34:52 +0000
commit6629b4bbf810e5d2e9323651acf8afb2936cf10b (patch)
treeb1a33f9d8233f4dc8de449a51a802fc5f68d7b1b /src/drivers/intel
parent7f1e9dbf3a951599cfa0b2decf0bb6540a666cbd (diff)
downloadcoreboot-6629b4bbf810e5d2e9323651acf8afb2936cf10b.tar.xz
soc/intel/apollolake: Reset GPI IS & IE registers at ramstage
Reset GPI Interrupt status and enable registers from ramstage instead of bootblock so that it applies to devices in field. BUG=b:130593883 BRANCH=octopus TEST=Ensure that the Interrupt status & enable registers are reset during the boot up when the system is brought out of G3, S5 & S3. Ensure that the system boots fine to ChromeOS. Change-Id: Ib11b580ceb23bd1fe789f549b667a8ced2d859a1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32534 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/intel')
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