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authorElyes HAOUAS <ehaouas@noos.fr>2018-12-27 09:42:58 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-12-28 13:13:46 +0000
commit6ece0adf8cb68c4d74093d15b647a2d541123e8a (patch)
tree1025c716f55b3111a3c88d0e853d41a6f938221d /src/drivers/intel
parent2ea751a5880ff35c6f645b79acc4d10068d5d74a (diff)
downloadcoreboot-6ece0adf8cb68c4d74093d15b647a2d541123e8a.tar.xz
intel/fsp1_0/cache_as_ram.inc: Use tabs instead of white spaces
Change-Id: I93cf734daefabe1f7cfaa5f49ba789ac04c8a635 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/drivers/intel')
-rw-r--r--src/drivers/intel/fsp1_0/cache_as_ram.inc86
1 files changed, 43 insertions, 43 deletions
diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc
index d08f582f82..8ac3595867 100644
--- a/src/drivers/intel/fsp1_0/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc
@@ -19,10 +19,10 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
- cmp $0, %eax
- je cache_as_ram
- mov $0xa0, %eax
- jmp .Lhlt
+ cmp $0, %eax
+ je cache_as_ram
+ mov $0xa0, %eax
+ jmp .Lhlt
cache_as_ram:
post_code(0x20)
@@ -31,75 +31,75 @@ cache_as_ram:
* Find the FSP binary in cbfs.
* Make a fake stack that has the return value back to this code.
*/
- lea fake_fsp_stack, %esp
- jmp find_fsp_bypass_prologue
+ lea fake_fsp_stack, %esp
+ jmp find_fsp_bypass_prologue
find_fsp_ret:
/* Save the FSP location */
- mov %eax, %ebp
- cmp $CONFIG_FSP_LOC, %eax
- jae find_fsp_ok
- mov $0xb0, %eax
- jmp .Lhlt
+ mov %eax, %ebp
+ cmp $CONFIG_FSP_LOC, %eax
+ jae find_fsp_ok
+ mov $0xb0, %eax
+ jmp .Lhlt
find_fsp_ok:
post_code(POST_FSP_TEMP_RAM_INIT)
/* Calculate entry into FSP */
- mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
- add 0x1c(%ebp), %eax /* add in the offset for the FSP base address */
+ mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
+ add 0x1c(%ebp), %eax /* add in the offset for the FSP base address */
/*
* Pass early init variables on a fake stack (no memory yet)
* as well as the return location
*/
- lea CAR_init_stack, %esp
+ lea CAR_init_stack, %esp
/* call FSP binary to setup temporary stack */
- jmp *%eax
+ jmp *%eax
CAR_init_done:
- addl $4, %esp
- cmp $0, %eax
- je car_init_ok
- add $0xc0, %eax
- jmp .Lhlt
+ addl $4, %esp
+ cmp $0, %eax
+ je car_init_ok
+ add $0xc0, %eax
+ jmp .Lhlt
car_init_ok:
/* Save FSP_INFO_HEADER location in ebx */
- mov %ebp, %ebx
+ mov %ebp, %ebx
/*
* set up bootloader stack
* ecx: stack base
* edx: stack top
*/
- mov %edx, %esp
- movl %esp, %ebp
+ mov %edx, %esp
+ movl %esp, %ebp
/* Clear the cbmem CAR memory region. */
- movl %ecx, %edi
- movl %edx, %ecx
- sub %edi, %ecx
- shr $2, %ecx
- xorl %eax, %eax
- rep stosl
+ movl %ecx, %edi
+ movl %edx, %ecx
+ sub %edi, %ecx
+ shr $2, %ecx
+ xorl %eax, %eax
+ rep stosl
before_romstage:
post_code(0x23)
/* Call romstage.c main function. */
- pushl %ebx /* main takes FSP_INFO_HEADER as its argument */
- call main /* does not return */
- movb $0xB8, %ah
- jmp .Lhlt
+ pushl %ebx /* main takes FSP_INFO_HEADER as its argument */
+ call main /* does not return */
+ movb $0xB8, %ah
+ jmp .Lhlt
.Lhlt:
#if IS_ENABLED(CONFIG_POST_IO)
- outb %al, $CONFIG_POST_IO_PORT
+ outb %al, $CONFIG_POST_IO_PORT
#endif
hlt
- jmp .Lhlt
+ jmp .Lhlt
/*
* esp is set to this location so that the call into and return from the FSP
@@ -107,17 +107,17 @@ before_romstage:
*/
.align 4
fake_fsp_stack:
- .long find_fsp_ret
+ .long find_fsp_ret
CAR_init_params:
- .long dummy_microcode
- .long 0
- .long CACHE_ROM_BASE /* Firmware Location */
- .long CACHE_ROM_SIZE /* Total Firmware Length */
+ .long dummy_microcode
+ .long 0
+ .long CACHE_ROM_BASE /* Firmware Location */
+ .long CACHE_ROM_SIZE /* Total Firmware Length */
CAR_init_stack:
- .long CAR_init_done
- .long CAR_init_params
+ .long CAR_init_done
+ .long CAR_init_params
dummy_microcode:
- .long 0
+ .long 0