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authorMohan D'Costa <mohan@ndr.co.jp>2014-09-18 15:57:06 +0900
committerMartin Roth <gaumless@gmail.com>2014-09-29 19:35:57 +0200
commited0c83877f453b94a5e68bef62d6dbba1b97f0d2 (patch)
treec0c3ba635505da345f65840cb2270556e7f13c19 /src/drivers/intel
parentbdae9bedcdf5650abee089564c47ecbf2ba70f79 (diff)
downloadcoreboot-ed0c83877f453b94a5e68bef62d6dbba1b97f0d2.tar.xz
intel/fsp_baytrail: Add S3 suspend/resume Support
This adds S3 Suspend / Resume support to Intel's Bay Trail FSP It is based on the "src/soc/intel/baytrail/romstage/romstage.c" implementation. Change-Id: If0011068eb7290d1b764c5c4b12c17375fb69008 Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp> Reviewed-on: http://review.coreboot.org/6937 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/drivers/intel')
-rw-r--r--src/drivers/intel/fsp/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp/Kconfig b/src/drivers/intel/fsp/Kconfig
index 5e4404646e..2d41365320 100644
--- a/src/drivers/intel/fsp/Kconfig
+++ b/src/drivers/intel/fsp/Kconfig
@@ -63,6 +63,7 @@ config ENABLE_FSP_FAST_BOOT
config ENABLE_MRC_CACHE
bool
+ default y if HAVE_ACPI_RESUME
default n
help
Enabling this feature will cause MRC data to be cached in NV storage.