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| author | Alexander Couzens <lynxis@fe80.eu> | 2018-08-23 16:40:55 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-30 14:45:23 +0000 |
| commit | 661907cdb4eda6c3d0044895b4cccfc10b6bd8ac (patch) | |
| tree | 7d0b8fdb26b35c479dc86aba5ed5d6d661c8bc20 /src/drivers/intel | |
| parent | 6bbfb3bfd62e2d19b410c12b429eabc1f329833a (diff) | |
| download | coreboot-661907cdb4eda6c3d0044895b4cccfc10b6bd8ac.tar.xz | |
drivers/intel/gma: store uint8_t brightness values in mailbox3
The _BCM function requires a percentage value. While the
brightness in mailbox3 requires a value in uint8_t. Meaning 255 = 100%.
Previous implementation stored the percentage brightness value resulting
in limiting the brightness to ~40% of it's maximum power.
Only affects brightness control using mailbox3.
Fixes: 6838aaebf9ec ("drvs/intel/gma/acpi: Add methods to use MBOX3")
Change-Id: I290b5f5b2a8ee406e39e86d3e0de9997798d890d
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/28345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/gma/acpi/configure_brightness_levels.asl | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl index 8625f04a9f..0867c5ae06 100644 --- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl +++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl @@ -69,7 +69,14 @@ Return (Ones) } - Store (Or (Arg0, 0x80000000), BCLP) + /* BCLP requires brightness unsigned 8bit. 255 = 100 % */ + Store (Divide (Multiply (Arg0, 255), 100), Local1) + If (LGreater(Local1, 255)) { + Store (255, Local1) + } + /* set valid bit */ + Store (Or (Local1, 0x80000000), BCLP) + /* Request back-light change */ Store (0x2, ASLC) /* Trigger IRQ */ |