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| author | Nicola Corna <nicola@corna.info> | 2018-04-02 10:27:06 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-05-02 14:14:50 +0000 |
| commit | e134db253589cff2f8c4cfba171a18c75430aad8 (patch) | |
| tree | 9713ef34588fcd95f4b94575bf5bc0f0e657ff22 /src/drivers/intel | |
| parent | b645ab6f07469c9db40ebd0442e221cbf9c1bfae (diff) | |
| download | coreboot-e134db253589cff2f8c4cfba171a18c75430aad8.tar.xz | |
mb/sapphire/pureplatinumh61: Use custom SPI OPMENU
The SPI chip in this board needs a custom OPMENU, otherwise flashrom
fails halfway during the write.
From the default OPMENU, Block Erase (0xd8) has been replaced by AAI
write (0xad) and Fast Read (0x0b) by Write Disable (0x04).
Change-Id: Ie18ee4e32511482dab747c9ffeac60d3994df320
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/25551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/drivers/intel')
0 files changed, 0 insertions, 0 deletions