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authorAndrey Petrov <andrey.petrov@intel.com>2016-02-25 14:16:33 -0800
committerMartin Roth <martinroth@google.com>2016-03-08 13:43:04 +0100
commit465fc13c0e69ddcf38168b62104fca37b91bdd68 (patch)
tree3dcb54f8fbe08460f808157ef1f242da28b03403 /src/drivers/intel
parent6321d7c14bf96719d199cfe921d4299c93cd441f (diff)
downloadcoreboot-465fc13c0e69ddcf38168b62104fca37b91bdd68.tar.xz
drivers/intel/fsp2_0: Add MemoryInit API
This adds implementation of fsp_memory_init() that is used to train memory. Change-Id: I72268aaa91eea7e4d4f072d70a47871d74c2b979 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13798 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel')
-rw-r--r--src/drivers/intel/fsp2_0/include/fsp/api.h11
-rw-r--r--src/drivers/intel/fsp2_0/include/fsp/info_header.h14
-rw-r--r--src/drivers/intel/fsp2_0/memory_init.c73
3 files changed, 77 insertions, 21 deletions
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 0d45df3ebd..c098a5b143 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -16,6 +16,8 @@
#include <stddef.h>
#include <memrange.h>
#include <fsp/info_header.h>
+#include <soc/fsp/FspmUpd.h>
+#include <soc/fsp/FspsUpd.h>
enum fsp_status {
FSP_SUCCESS = 0x00000000,
@@ -39,19 +41,14 @@ enum fsp_notify_phase {
};
-/* Opaque structures. These are platform-specific. */
-struct FSP_M_CONFIG;
-struct FSP_S_CONFIG;
-
/* Main FSP stages */
enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *r);
enum fsp_status fsp_silicon_init(struct range_entry *r);
enum fsp_status fsp_notify(enum fsp_notify_phase phase);
/* Callbacks for updating stage-specific parameters */
-void platform_fsp_memory_init_params_cb(struct fsp_m_arch_upd *archupd,
- struct FSP_M_CONFIG *mcfg);
-void platform_fsp_silicon_init_params_cb(struct FSP_S_CONFIG *silupd);
+void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd);
+void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd);
/*
* # DOCUMENTATION:
diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
index 0f25496008..468101e266 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
@@ -39,20 +39,6 @@ struct fsp_header {
uint8_t revision;
};
-struct fsp_upd_header {
- uint64_t signature;
- uint8_t revision;
-};
-
-struct fsp_m_arch_upd {
- uint8_t revision;
- uintptr_t nvs_buffer;
- uintptr_t stack_base;
- uint32_t stack_size;
- uint32_t bootloader_tolumsz;
- uint32_t boot_mode;
-};
-
enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob);
void fsp_print_header_info(const struct fsp_header *hdr);
void fsp_print_upd_info(const struct fsp_header *hdr, void *cfg_blob);
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
new file mode 100644
index 0000000000..8033937455
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/io.h>
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <memrange.h>
+#include <string.h>
+#include <timestamp.h>
+
+typedef asmlinkage enum fsp_status (*fsp_memory_init_fn)
+ (void *raminit_upd, void **hob_list);
+
+static enum fsp_status do_fsp_memory_init(void **hob_list_ptr,
+ struct fsp_header *hdr)
+{
+ enum fsp_status status;
+ fsp_memory_init_fn fsp_raminit;
+ struct FSPM_UPD fspm_upd, *upd;
+
+ post_code(0x34);
+
+ upd = (struct FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base);
+
+ if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) {
+ printk(BIOS_ERR, "Invalid FSPM signature\n");
+ return FSP_INCOMPATIBLE_VERSION;
+ }
+
+ /* Copy the default values from the UPD area */
+ memcpy(&fspm_upd, upd, sizeof(fspm_upd));
+
+ /* Give SoC and mainboard a chance to update the UPD */
+ platform_fsp_memory_init_params_cb(&fspm_upd);
+
+ /* Call FspMemoryInit */
+ fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
+ printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit);
+ printk(BIOS_SPEW, "\t%p: raminit_upd\n", &fspm_upd);
+ printk(BIOS_SPEW, "\t%p: hob_list ptr\n", hob_list_ptr);
+
+ timestamp_add_now(TS_FSP_MEMORY_INIT_START);
+ status = fsp_raminit(&fspm_upd, hob_list_ptr);
+ post_code(0x37);
+ timestamp_add_now(TS_FSP_MEMORY_INIT_END);
+
+ printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
+
+ return status;
+}
+
+enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *range)
+{
+ struct fsp_header hdr;
+
+ /* TODO: do not hardcode CBFS file names */
+ if (fsp_load_binary(&hdr, "blobs/fspm.bin", range) != CB_SUCCESS)
+ return FSP_NOT_FOUND;
+
+ return do_fsp_memory_init(hob_list, &hdr);
+}