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| author | Martin Roth <martinroth@google.com> | 2017-07-21 17:10:15 +0000 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-21 17:39:10 +0000 |
| commit | 80358a1f478713861a3e66874a1ffb7cf259bd7c (patch) | |
| tree | 86c1eff35d648726a2e93617aa2780fb64482028 /src/drivers/intel | |
| parent | 70de396958627680a16992fbb8c5e6652dd35bf4 (diff) | |
| download | coreboot-80358a1f478713861a3e66874a1ffb7cf259bd7c.tar.xz | |
Revert "soc/intel/cannonlake: Add postcar stage support"
This reverts commit 399c022a8c6cba7ad6d75fdf377a690395877611.
This was merged too early. I'll repost it.
Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20686
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp2_0/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index d5709adc31..cdf6146d51 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -43,7 +43,6 @@ postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c postcar-$(CONFIG_FSP_CAR) += util.c postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c -postcar-y += hand_off_block.c CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include |