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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-09-07 01:54:23 -0700 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-09-07 17:40:32 +0000 |
| commit | 2c482a969a546a70c2787d4d96d1ac212da11eff (patch) | |
| tree | 2e255af6918f41ae63e185726ae7620a598fcc49 /src/drivers/intel | |
| parent | 4460703f59c58626c762a8a1244842b7a3efe0db (diff) | |
| download | coreboot-2c482a969a546a70c2787d4d96d1ac212da11eff.tar.xz | |
intel: Do not hardcode the position of mrc.cache
The reason for hardcoding the position of the MRC cache was to satisfy
the alignment to the erase size of the flash chip. Hardcoding is no
longer needed, as we can specify alignment directly. In the long term,
the MRC cache will have to move to FMAP, but for now, we reduce
fragmentation in CBFS.
Note that soc/intel/common hardcoding of mrc.cache is not removed, as
the mrc cache implementation there does not use CBFS to find the cache
region, and needs a hardcoded address.
Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11527
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp1_0/Kconfig | 11 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_0/Makefile.inc | 2 |
2 files changed, 1 insertions, 12 deletions
diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index 020235aab8..8d3bf4c901 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -82,17 +82,6 @@ config MRC_CACHE_SIZE should be a full sector of the flash ROM chip and nothing else should be included in CBFS in any sector that the fast boot cache data is in. -config MRC_CACHE_LOC - hex "Fast Boot Data Cache location in CBFS" - default 0xfff50000 - depends on ENABLE_MRC_CACHE - help - The location in CBFS for the MRC data to be cached. - - WARNING: This should be on a sector boundary of the BIOS ROM chip - and nothing else should be included in that sector, or IT WILL BE - ERASED. - config VIRTUAL_ROM_SIZE hex "Virtual ROM Size" default ROM_SIZE diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index ddc6bef926..11ff31aada 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -42,6 +42,6 @@ $(obj)/mrc.cache: cbfs-files-y += mrc.cache mrc.cache-file := $(obj)/mrc.cache -mrc.cache-position := $(CONFIG_MRC_CACHE_LOC) +mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif |