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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-01-29 14:35:13 -0800 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-02-02 19:00:35 +0100 |
| commit | 95909924024687d42cdf34518d34d7c8eb1aee57 (patch) | |
| tree | 7e536d1a0d45009527bcf7db53c873b4d4dfc4a5 /src/drivers/intel | |
| parent | 05c0215ff31c80a06e3824fb55f5983b62f894cd (diff) | |
| download | coreboot-95909924024687d42cdf34518d34d7c8eb1aee57.tar.xz | |
soc/intel/common: Use SoC specific routine to read/write MTRRs
The registers associated with the MTRRs for Quark are referenced through
a port on the host bridge. Support the standard configurations by
providing a weak routines which just do a rdmsr/wrmsr.
Testing:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select DISPLAY_MTRRS"
* Add "select HAVE_FSP_PDAT_FILE"
* Add "select HAVE_FSP_RAW_BIN"
* Add "select HAVE_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* The MTRRs are displayed and
* The message "FspTempRamExit returned successfully" is displayed
TEST=Build and run on Galileo
Change-Id: If2fea66d4b054be4555f5f172ea5945620648325
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13529
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp1_1/after_raminit.S | 13 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/romstage.h | 7 |
2 files changed, 20 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index eb99157959..122c0bf03e 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -87,6 +87,13 @@ * +0: Number of variable MTRRs to clear */ +#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS) + push %esp + call soc_set_mtrrs + + /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */ + movl %eax, %esp +#else /* Clear all of the variable MTRRs. */ popl %ebx movl $MTRR_PHYS_BASE(0), %ecx @@ -129,6 +136,8 @@ dec %ebx jmp 2b 2: +#endif /* CONFIG_SOC_SETS_MTRRS */ + post_code(0x39) /* And enable cache again after setting MTRRs. */ @@ -138,11 +147,15 @@ post_code(0x3a) +#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS) + call soc_enable_mtrrs +#else /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr orl $MTRR_DEF_TYPE_EN, %eax wrmsr +#endif /* CONFIG_SOC_SETS_MTRRS */ post_code(0x3b) diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 4683f5e5a2..d07dc375c8 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -88,4 +88,11 @@ void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd); void soc_pre_ram_init(struct romstage_params *params); +/* + * Set the MTRRs using the data on the stack from setup_stack_and_mtrrs. + * Return a new top_of_stack value which removes the setup_stack_and_mtrrs data. + */ +asmlinkage void *soc_set_mtrrs(void *top_of_stack); +asmlinkage void soc_enable_mtrrs(void); + #endif /* _COMMON_ROMSTAGE_H_ */ |