diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-08-26 14:58:29 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-10 09:43:13 +0000 |
| commit | a887492e1e51849b75c7bb0d67430be4b1074493 (patch) | |
| tree | 37d52033d2b8f0cde47851cf0a8e71c38dec88c6 /src/drivers/intel | |
| parent | a7c609c262d5beba968519903fed297dc4b601c1 (diff) | |
| download | coreboot-a887492e1e51849b75c7bb0d67430be4b1074493.tar.xz | |
FSP: Pass FSP image base address to find_fsp
Add a parameter to find_fsp which is the image base address. Adjust the
fake stack in cache_as_ram.inc to pass in the read-only FSP image base
address. In fsp_notify, pass in the read-only FSP image base address
when the FSP header pointer is NULL. In find_fsp, validate the FSP
binary image starting from the specified image base address.
BRANCH=none
BUG=None
TEST=Build and run on Skylake
Change-Id: Iac43c8aac8491390479af551765b514ca919928a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 592dae53f3b32694190cc5cb0fa6ca94df68aa95
Original-Change-Id: I7d6a415458a81f3b6bcdcfc9a90eceb2ac22144e
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295593
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11545
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp1_1/cache_as_ram.inc | 1 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/fsp_util.c | 8 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/fsp_util.h | 2 |
3 files changed, 6 insertions, 5 deletions
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 6af30ce5e5..d4df67b6ed 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -342,6 +342,7 @@ halt3: .align 4 fake_fsp_stack: .long find_fsp_ret + .long CONFIG_FSP_LOC /* FSP base address */ CAR_init_params: .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 1d67e78d07..e6e3889eb4 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -25,7 +25,7 @@ #include <timestamp.h> /* Locate the FSP binary in the coreboot filesystem */ -FSP_INFO_HEADER *find_fsp(void) +FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address) { union { EFI_FFS_FILE_HEADER *ffh; @@ -47,7 +47,7 @@ FSP_INFO_HEADER *find_fsp(void) for (;;) { /* Get the FSP binary base address in CBFS */ - fsp_ptr.u8 = (u8 *)CONFIG_FSP_LOC; + fsp_ptr.u32 = fsp_base_address; /* Check the FV signature, _FVH */ if (fsp_ptr.fvh->Signature != 0x4856465F) { @@ -81,7 +81,7 @@ FSP_INFO_HEADER *find_fsp(void) fsp_ptr.u8 += sizeof(EFI_RAW_SECTION); /* Verify that the FSP base address.*/ - if (fsp_ptr.fih->ImageBase != CONFIG_FSP_LOC) { + if (fsp_ptr.fih->ImageBase != fsp_base_address) { fsp_ptr.u8 = (u8 *)ERROR_IMAGEBASE_MISMATCH; break; } @@ -150,7 +150,7 @@ void fsp_notify(u32 phase) fsp_header_ptr = fsp_get_fih(); if (fsp_header_ptr == NULL) { - fsp_header_ptr = (void *)find_fsp(); + fsp_header_ptr = (void *)find_fsp(CONFIG_FSP_LOC); if ((u32)fsp_header_ptr < 0xff) { /* output something in case there is no serial */ post_code(0x4F); diff --git a/src/drivers/intel/fsp1_1/fsp_util.h b/src/drivers/intel/fsp1_1/fsp_util.h index 8f6f77a6e7..51ecb98f2c 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.h +++ b/src/drivers/intel/fsp1_1/fsp_util.h @@ -42,7 +42,7 @@ #include <soc/chipset_fsp_util.h> /* find_fsp() should only be called from assembly code. */ -FSP_INFO_HEADER *find_fsp(void); +FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address); /* Set FSP's runtime information. */ void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list); /* Use a new FSP_INFO_HEADER at runtime. */ |