diff options
| author | Alexandru Gagniuc <alexandrux.gagniuc@intel.com> | 2016-05-23 12:16:58 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-05-26 23:50:02 +0200 |
| commit | c4ea8f7d3fb56b43482b8abd8405280f50d98864 (patch) | |
| tree | ff8598d2a4e12b65a2233e549d4a1f442f030428 /src/drivers/intel | |
| parent | c16918ac11c32338ba99656ec47ca05e26a731ac (diff) | |
| download | coreboot-c4ea8f7d3fb56b43482b8abd8405280f50d98864.tar.xz | |
drivers/intel/fsp2_0: Send post codes around calls to the blobs
By design, FSP will send POST codes to port 80. In this case we have
both coreboot and FSP pushing post codes, which may make debugging
harder. In order to get a clear picture of where FSP execution begins
and ends, send post codes before and after any call to the FSP blobs.
Note that sending a post code both before and after is mostly useful
on chromeec enabled boards, where the EC console will provide a
historic list of post codes.
Change-Id: Icfd22b4f6d9e91b01138f97efd711d9204028eb1
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14951
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp2_0/memory_init.c | 3 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/notify.c | 14 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/silicon_init.c | 2 |
3 files changed, 14 insertions, 5 deletions
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index c1c2fe4670..45516aa731 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -51,9 +51,10 @@ static enum fsp_status do_fsp_memory_init(void **hob_list_ptr, printk(BIOS_SPEW, "\t%p: raminit_upd\n", &fspm_upd); printk(BIOS_SPEW, "\t%p: hob_list ptr\n", hob_list_ptr); + post_code(POST_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_START); status = fsp_raminit(&fspm_upd, hob_list_ptr); - post_code(0x37); + post_code(POST_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index d9de02235e..bd489d4ce6 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -38,17 +38,23 @@ enum fsp_status fsp_notify(enum fsp_notify_phase phase) printk(BIOS_DEBUG, "FspNotify %x\n", (uint32_t) phase); - if (phase == AFTER_PCI_ENUM) + if (phase == AFTER_PCI_ENUM) { timestamp_add_now(TS_FSP_BEFORE_ENUMERATE); - else if (phase == READY_TO_BOOT) + post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE); + } else if (phase == READY_TO_BOOT) { timestamp_add_now(TS_FSP_BEFORE_FINALIZE); + post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE); + } ret = fspnotify(¬ify_params); - if (phase == AFTER_PCI_ENUM) + if (phase == AFTER_PCI_ENUM) { timestamp_add_now(TS_FSP_AFTER_ENUMERATE); - else if (phase == READY_TO_BOOT) + post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE); + } else if (phase == READY_TO_BOOT) { timestamp_add_now(TS_FSP_AFTER_FINALIZE); + post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE); + } return ret; } diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 18aded544f..f1deed78d8 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -42,10 +42,12 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) platform_fsp_silicon_init_params_cb(&upd); timestamp_add_now(TS_FSP_SILICON_INIT_START); + post_code(POST_FSP_SILICON_INIT); silicon_init = (void *) (hdr->image_base + hdr->silicon_init_entry_offset); status = silicon_init(&upd); timestamp_add_now(TS_FSP_SILICON_INIT_END); + post_code(POST_FSP_SILICON_INIT); printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); return status; |