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authorVincent Palatin <vpalatin@chromium.org>2012-08-07 16:05:14 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-07 03:57:47 +0100
commitfc1b9ee4aa19e698b07aaa050949b791aa119847 (patch)
tree90e679ac91f9dc9c3a0ebe55cbb50d4085473125 /src/drivers/pc80
parent6f4297677c130cd181b107ed496874f7b21ee343 (diff)
downloadcoreboot-fc1b9ee4aa19e698b07aaa050949b791aa119847.tar.xz
rtc: force mc146818 register D to a correct value
On Panther Point PCH (and maybe cougar point), when some of the register D reserved bits are set, the RTC starts misbehaving (e.g. incrementing the year byte every second). There are probably undocumented features implemented behind those bits. Let's reset register D to a known state to ensure we get the expected RTC behavior. Change-Id: I7e2c2a2c6130a974bccb3d760b41eaa579a58b67 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: http://review.coreboot.org/1695 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/drivers/pc80')
-rw-r--r--src/drivers/pc80/mc146818rtc.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c
index cc14a412dc..efeb378d31 100644
--- a/src/drivers/pc80/mc146818rtc.c
+++ b/src/drivers/pc80/mc146818rtc.c
@@ -171,6 +171,8 @@ void rtc_init(int invalid)
cmos_write(RTC_CONTROL_DEFAULT, RTC_CONTROL);
/* Setup the frequency it operates at */
cmos_write(RTC_FREQ_SELECT_DEFAULT, RTC_FREQ_SELECT);
+ /* Ensure all reserved bits are 0 in register D */
+ cmos_write(RTC_VRT, RTC_VALID);
#if CONFIG_USE_OPTION_TABLE
/* See if there is a LB CMOS checksum error */