drivers/spi: Pass flash parameters from coreboot to payload

A payload may want to run erase operations on SPI NOR flash without
re-probing the device to get its properties. This patch passes up
three properties of flash to achieve that:
- The size of the flash device
- The sector size, i.e., the granularity of erase
- The command used for erase
The patch sends the parameters through coreboot and then libpayload.
The patch also includes a minor refactoring of the flash erase code.
Parameters are sent up for just one flash device. If multiple SPI
flash devices are probed, the second one will "win" and its
parameters will be sent up to the payload.

TEST=Observed parameters to be passed up to depthcharge through
libpayload and be used to correctly initialize flash and do an erase.
TEST=Winbond and Gigadevices spi flash drivers compile with the changes;
others don't, for seemingly unrelated reasons.
BRANCH=none
BUG=chromium:446377

Change-Id: Ib8be86494b5a3d1cfe1d23d3492e3b5cba5f99c6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126
Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72
Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/239570
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9726
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 41 insertions, 3 deletions

diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
index 607fb214a8..8213e852be 100644
--- a/src/drivers/spi/spi_flash.c
+++ b/src/drivers/spi/spi_flash.c
@@ -7,6 +7,7 @@
  * Licensed under the GPL-2 or later.
  */
 
+#include <cbfs.h>
 #include <cpu/x86/smm.h>
 #include <delay.h>
 #include <stdlib.h>
@@ -17,6 +18,8 @@
 #include "spi_flash_internal.h"
 #include <timer.h>
 
+static struct spi_flash *spi_flash_dev = NULL;
+
 static void spi_flash_addr(u32 addr, u8 *cmd)
 {
 	/* cmd[0] is actual command */
@@ -186,8 +189,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
 		CMD_READ_STATUS, STATUS_WIP);
 }
 
-int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd,
-			u32 offset, size_t len)
+int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
 {
 	u32 start, end, erase_size;
 	int ret;
@@ -201,7 +203,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd,
 
 	flash->spi->rw = SPI_WRITE_FLAG;
 
-	cmd[0] = erase_cmd;
+	cmd[0] = flash->erase_cmd;
 	start = offset;
 	end = start + len;
 
@@ -376,9 +378,45 @@ flash_detected:
 	printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n",
 			flash->name, flash->sector_size, flash->size);
 
+	spi_flash_dev = flash;
+
 	return flash;
 
 err_manufacturer_probe:
 err_read_id:
 	return NULL;
 }
+
+/* Only the RAM stage will build in the lb_new_record symbol
+ * so only define this function if we are after that stage */
+#ifdef __RAMSTAGE__
+
+void lb_spi_flash(struct lb_header *header)
+{
+	struct lb_spi_flash *flash;
+
+	flash = (struct lb_spi_flash *)lb_new_record(header);
+
+	flash->tag = LB_TAG_SPI_FLASH;
+	flash->size = sizeof(*flash);
+
+	/* Try to get the flash device if not loaded yet */
+	if (!spi_flash_dev) {
+		struct cbfs_media media;
+		init_default_cbfs_media(&media);
+	}
+
+	if (spi_flash_dev) {
+		flash->flash_size = spi_flash_dev->size;
+		flash->sector_size = spi_flash_dev->sector_size;
+		flash->erase_cmd = spi_flash_dev->erase_cmd;
+	} else {
+		flash->flash_size = CONFIG_ROM_SIZE;
+		/* Default 64k erase command should work on most flash.
+		 * Uniform 4k erase only works on certain devices. */
+		flash->sector_size = 64 * KiB;
+		flash->erase_cmd = CMD_BLOCK_ERASE;
+	}
+}
+
+#endif