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authorFurquan Shaikh <furquan@google.com>2020-03-26 15:45:58 -0700
committerFurquan Shaikh <furquan@google.com>2020-04-02 16:54:19 +0000
commit35bff432e5456acec8e68adca6b496fda53c6c57 (patch)
tree06bace7021fc980ba381805da7a049f857e7207d /src/drivers/spi
parent5b1f335ef8aed95e01f040bc7074fb00acc8ab7e (diff)
downloadcoreboot-35bff432e5456acec8e68adca6b496fda53c6c57.tar.xz
soc/intel/tigerlake: Add macros and SPD information for DDR4
This change adds new memory topologies (SODIMM, MIXED) that are supported by DDR4 and macros required for DDR4 support. Memory initialization support for DDR4 will be added in a follow-up change. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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