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authorPhilipp Hug <philipp@hug.cx>2018-07-07 21:34:31 +0200
committerRonald G. Minnich <rminnich@gmail.com>2018-09-13 15:32:53 +0000
commit7524400242be26610df143b5d1d781f875239c45 (patch)
treea8055581b7f492e2bddbb8937f7649c043db33bd /src/drivers/uart
parent3e51d530645059093e6dd27c4bbfafb8a216cd41 (diff)
downloadcoreboot-7524400242be26610df143b5d1d781f875239c45.tar.xz
uart/sifive: make divisor configurable
The SiFive UART on the HiFive Unleashed uses the tlclk as input clock which runs at coreclk / 2. The input frequency is configured in the board code depending on the current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz) Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'src/drivers/uart')
-rw-r--r--src/drivers/uart/sifive.c15
1 files changed, 11 insertions, 4 deletions
diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c
index dd47cafcf1..ce8ead0d05 100644
--- a/src/drivers/uart/sifive.c
+++ b/src/drivers/uart/sifive.c
@@ -46,11 +46,10 @@ struct sifive_uart_registers {
#define IP_TXWM BIT(0)
#define IP_RXWM BIT(1)
-void uart_init(int idx)
+static void sifive_uart_init(struct sifive_uart_registers *regs, int div)
{
- struct sifive_uart_registers *regs = uart_platform_baseptr(idx);
-
- /* TODO: Configure the divisor */
+ /* Configure the divisor */
+ write32(&regs->div, div);
/* Enable transmission, one stop bit, transmit watermark at 1 */
write32(&regs->txctrl, TXCTRL_TXEN|TXCTRL_NSTOP(1)|TXCTRL_TXCNT(1));
@@ -59,6 +58,14 @@ void uart_init(int idx)
write32(&regs->rxctrl, RXCTRL_RXEN|RXCTRL_RXCNT(0));
}
+void uart_init(int idx)
+{
+ unsigned int div;
+ div = uart_baudrate_divisor(get_uart_baudrate(),
+ uart_platform_refclk(), uart_input_clock_divider());
+ sifive_uart_init(uart_platform_baseptr(idx), div);
+}
+
static bool uart_can_tx(struct sifive_uart_registers *regs)
{
return !(read32(&regs->txdata) & TXDATA_FULL);