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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-26 22:33:51 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-30 11:07:46 +0000 |
| commit | e088721f715602df84503c960deb562064af5718 (patch) | |
| tree | 9a18a999885cdbe7f5355bf8cdd73f8d03062162 /src/drivers/uart | |
| parent | 1463a2a04d4ffcf7afbb7870502bf65d4ebcdca1 (diff) | |
| download | coreboot-e088721f715602df84503c960deb562064af5718.tar.xz | |
device,drivers/: Drop some __SIMPLE_DEVICE__ use
The simple PCI config accessors are always available
under names pci_s_[read|write]_configX.
Change-Id: Ic1b67695b7f72e4f1fa29e2d56698276b15024e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/drivers/uart')
| -rw-r--r-- | src/drivers/uart/oxpcie_early.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index b99040116a..eb6f8804a0 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ - #include <stdint.h> #include <stddef.h> #include <device/pci_ops.h> @@ -31,7 +29,7 @@ int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) { pci_devfn_t device = PCI_DEV(bus, dev, 0); - u32 id = pci_read_config32(device, PCI_VENDOR_ID); + u32 id = pci_s_read_config32(device, PCI_VENDOR_ID); switch (id) { case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */ /* On this device function 0 is the parallel port, and @@ -39,7 +37,7 @@ int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) * the UART. */ device = PCI_DEV(bus, dev, 3); - id = pci_read_config32(device, PCI_VENDOR_ID); + id = pci_s_read_config32(device, PCI_VENDOR_ID); if (id != 0xc11b1415) return -1; break; @@ -56,12 +54,12 @@ int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) return -1; /* Setup base address on device */ - pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); + pci_s_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); /* Enable memory on device */ - u16 reg16 = pci_read_config16(device, PCI_COMMAND); + u16 reg16 = pci_s_read_config16(device, PCI_COMMAND); reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(device, PCI_COMMAND, reg16); + pci_s_write_config16(device, PCI_COMMAND, reg16); car_set_var(oxpcie_present, 1); return 0; |