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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-07-30 09:01:24 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-08-07 12:36:35 +0000
commit6aea6f7a6b524d86be4fbdaf434aeda6d9f721a9 (patch)
tree6f21683e7f8fcf3462e0981d433c50ad805a15f9 /src/drivers/usb
parent6683e409d3688217e70f1f19deab152790b0f495 (diff)
downloadcoreboot-6aea6f7a6b524d86be4fbdaf434aeda6d9f721a9.tar.xz
usbdebug: Force EHCI to D0 state
When resuming from ACPI S3 suspend, EHCI controller may be in D3 power-management state. Bring it to D0 early so it is functional for console. NOTE: D3hot->D0 transition was observed to reset previous programming of PCI_COMMAND register. Change-Id: Id177ce61926beb057fe67ba42a306d8e565d2657 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/drivers/usb')
-rw-r--r--src/drivers/usb/pci_ehci.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c
index 9099976ad5..73c709cdd8 100644
--- a/src/drivers/usb/pci_ehci.c
+++ b/src/drivers/usb/pci_ehci.c
@@ -44,6 +44,15 @@ int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset)
if (class != PCI_EHCI_CLASSCODE)
return -1;
+ u8 pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM);
+ if (pm_cap) {
+ u16 pm_ctrl = pci_read_config16(dev, pm_cap + PCI_PM_CTRL);
+ /* Set to D0 and disable PM events. */
+ pm_ctrl &= ~PCI_PM_CTRL_PME_ENABLE;
+ pm_ctrl &= ~PCI_PM_CTRL_STATE_MASK;
+ pci_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl);
+ }
+
u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG);
if (!pos)
return -1;