diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2016-10-04 10:53:32 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-07 18:05:30 +0200 |
| commit | 028200f75f6d8d0f947d68f41ca10fbfe05f9283 (patch) | |
| tree | c56f256737b61702dbab15e0ba53a6c0766c8342 /src/drivers | |
| parent | 35c01bc4e0bc72d4ba8bafc922b47f9aa47ca02d (diff) | |
| download | coreboot-028200f75f6d8d0f947d68f41ca10fbfe05f9283.tar.xz | |
x86/acpi_device: Add support for GPIO output polarity
Instead of hard-coding the polarity of the GPIO to active high/low,
accept it as a parameter in devicetree. This polarity can then be used
while calling into acpi_dp_add_gpio to determine the active low status
correctly.
BUG=chrome-os-partner:55988
BRANCH=None
TEST=Verified that correct polarity is set for reset-gpio on reef.
Change-Id: I4aba4bb8bd61799962deaaa11307c0c5be112919
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/16877
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/drivers')
| -rw-r--r-- | src/drivers/generic/max98357a/max98357a.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 25e5104129..4a057b51d5 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -55,7 +55,8 @@ static void max98357a_fill_ssdt(struct device *dev) /* This points to the first pin in the first gpio entry in _CRS */ path = acpi_device_path(dev); dp = acpi_dp_new_table("_DSD"); - acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0, 0); + acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0, + config->sdmode_gpio.polarity); acpi_dp_add_integer(dp, "sdmode-delay", config->sdmode_delay); acpi_dp_write(dp); |