diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-23 11:30:22 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-11-10 22:57:55 +0000 |
| commit | 12440ce63e3f96b32311f4ebde4ef0861dbcec02 (patch) | |
| tree | 65eb7ad04c4e2025fdc23c8d685c54fc4c8ab565 /src/drivers | |
| parent | 8256ca0e14e57b17b27a81b16f220c94d728e117 (diff) | |
| download | coreboot-12440ce63e3f96b32311f4ebde4ef0861dbcec02.tar.xz | |
drivers/intel/fsp1_1: Fake microcode update to make FSP happy
The FSP loops through microcode updates and at the end checks if
the microcode revision is not zero. Since we update the microcode
before loading FSP, this is the case and a fake microcode can be
passed to the FSP.
The advantage is that the Kconfig symbols to specify the location and
the size of the microcode blob can be dropped.
Change-Id: I63cfb7b19e9795da85566733fb4c1ff989e85d03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36255
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers')
| -rw-r--r-- | src/drivers/intel/fsp1_1/Kconfig | 13 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/cache_as_ram.S | 23 |
2 files changed, 21 insertions, 15 deletions
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 1d229520b8..5f8f5b5534 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -56,19 +56,6 @@ config FSP_LOC value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool). -config CPU_MICROCODE_CBFS_LEN - hex "Microcode update region length in bytes" - default 0x0 - help - The length in bytes of the microcode update region. - -config CPU_MICROCODE_CBFS_LOC - hex "Microcode update base address in CBFS" - default 0x0 - help - The location (base address) in CBFS that contains the microcode update - binary. - config DISPLAY_HOBS bool "Display hand-off-blocks (HOBs)" default n diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index f4638d9c18..fea7acb2e2 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -239,11 +239,30 @@ fake_fsp_stack: .long CONFIG_FSP_LOC /* FSP base address */ CAR_init_params: - .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ - .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ + .long fake_microcode /* Microcode Location */ + .long fake_microcode_end - fake_microcode /* Microcode Length */ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ .long CONFIG_ROM_SIZE /* Firmware Length */ CAR_init_stack: .long CAR_init_done .long CAR_init_params + + /* coreboot updates microcode itself. FSP still needs a pointer + to something that looks like microcode, so provide it with fake + microcode. */ +fake_microcode: +fake_microcode_header_start: + .long 1 /* Header Version */ + .long 1 /* Microcode revision */ + .long 0x10232019 /* Date: Time of writing 23-10-2019 */ + .long 0x00010ff0 /* Sig: (non existing) Family: 0xf, Model: 0x1f, stepping: 0 */ + .long 0 /* Checksum: not checked by FSP, so won't care */ + .long 1 /* Loader Revision */ + .long 1 /* Processor Flags */ + .long fake_microcode_end - fake_microcode_header_end /* Data Size */ + .long fake_microcode_end - fake_microcode /* Total Size */ + .space 12 /* Reserved */ +fake_microcode_header_end: + .space 0x10 /* 16 bytes of empty data */ +fake_microcode_end: |